• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.926-927
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• 2008

This paper presents the ZVZCS(Zero- Voltage and Zero-Current-Switching) Full-Bridge converter using the secondary coupled inductor and auxiliary capacitor. The converter with phase-shift control is proposed to reduce the circulating loss in primary and the voltage stress in secondary side. Using a coupled winding of the output inductor, two auxiliary capacitors are generated to reset the primary current at circulating interval.

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.320-323
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• 2001

A ZVZCS(Zero-Voltage and Zero-Current-Switching) Three Level DC/DC Converter is presented to secondary auxiliary circuit. The converter presented in this paper used a phase shift control with a flying capacitor in the primary side to achieve ZVS for the outer switch. A secondary auxiliary circuit, which consists of one small capacitor and two small diode, is added in the secondary to provides ZVZCS conditions to primary switches, and aids to clamp secondary rectifier voltage. The auxiliary circuit Includes neither lossy component nor addition active switch, which makes the proposed converter efficient and effective. The principle of operation, feature, and design considerations are illustrated and verified through the experiment with a 500W 50kHz prototype converter.

• Proceedings of the KIEE Conference
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• 2003.04a
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• pp.270-272
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• 2003

Switching power supplies are widely used in many industrial fields. Power factor correction(PFC) circuits have tendency to be applied in new power supply designs. The input active power factor correction(APFC) circuits can be implemented using either the two-stage approach or the single-stage approach. The single-stage PFC circuit has advantage to reduce the number of components by eliminating a need for the PFC switch and control circuit. However, unlike in the two-stage approach, the do voltage on the energy storage capacitor in a single-stage PFC circuit is not well regulated. As a result. in universal line application($90{\sim}265Vac$), the storage capacitor voltage varies with the load and line variation. In this paper, the performance of output voltage regulation and transient response are clarified here. The validity of designed boost PFC circuit is confirmed by MATLAB simulation and experimental results of 2 [kW] prototype converter.

• Proceedings of the KIEE Conference
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• 2000.07b
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• pp.1199-1201
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• 2000

This paper proposes a harmonics reducing circuit for fluorescent lamp inverters using hybrid type smoothing circuit with pumping and smoothing capacitors. A waveform of full-wave rectification used as a direct current power supply at fluorescent lamp inverters contains a lot of harmonic wave from inrush current which is generated near the maximum of input voltage with purse shape when voltage smoothing capacitor is charged. Therefore, in order to suppress inrush current which will result in harmonic wave. this paper proposes a method to control abrupt charging current by use of charging voltage at pumping capacitor. The suppression of harmonics generation at lamp current is confirmed through simulations.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.5
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• pp.51-59
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• 2003

The utility and many customers employ capacitor banks(STATCON so called at the utility) to help control the power factor(customers) or voltage(the utility) by supplying reactive power to inductive loads. This paper presents analysis of transient overvoltages and harmonics due to utility STATCON switching. One simple and inexpensive means of limiting the voltage magnification transient and reducing harmonics is to switch the capacitor banks on a few minutes after the STATCON has been switched. Simulation results used the EDSA software package show the effects of decreased the transient voltage and harmonic reduction at the customer. And also harmonic limits based on the well-known international harmonic standards IEEE 519 and IEC 1000 are evaluated for the customer.

• Korean Journal of Materials Research
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• v.29 no.2
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• pp.106-115
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• 2019

Recently, metal cases are widely used in smart phones for their luxurious color and texture. However, when a metal case is used, electric shock may occur during charging. Chip capacitors of various values are used to prevent the electric shock. However, chip capacitors are vulnerable to electrostatic discharge(ESD) generated by the human body, which often causes insulation breakdown during use. This breakdown can be eliminated with a high-voltage chip varistor over 340V, but when the varistor voltage is high, the capacitance is limited to about 2pF. If a chip capacitor with a high dielectric constant and a chip varistor with a high voltage can be combined, it is possible to obtain a new device capable of coping with electric shock and ESD with various capacitive values. Usually, varistors and capacitors differ in composition, which causes different shrinkage during co-firing, and therefore camber, internal crack, delamination and separation may occur after sintering. In addition, varistor characteristics may not be realized due to the diffusion of unwanted elements into the varistor during firing. Various elements are added to control shrinkage. In addition, a buffer layer is inserted in the middle of the varistor-capacitor junction to prevent diffusion during firing, thereby developing a co-fired product with desirable characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.2
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• pp.76-80
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• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• Journal of Power Electronics
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• v.18 no.2
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• pp.482-491
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• 2018

The practical design methodology of a three-phase dual active bridge (3ph-DAB) converter applied to low voltage direct current (LVDC) applications is proposed by using a mathematical model based on the steady-state operation. An analysis of the small-signal model (SSM) is important for the design of a proper controller to improve the stability and dynamics of the converter. The proposed lead-lag controller for the 3ph-DAB converter is designed with a simplified SSM analysis including an equivalent series resistor (ESR) for the output capacitor. The proposed controller can compensate the effects of the ESR zero of the output capacitor in the control-to-output voltage transfer function that can cause high-frequency noises. In addition, the performance of the power converter can be improved by using a controller designed by a SSM analysis without additional cost. The accuracy of the simplified SSM including the ESR zero of the output capacitor is verified by simulation software (PSIM). The design methodology of the 3ph-DAB converter and the performance of the proposed controller are verified by experimental results obtained with a 5-kW prototype 3ph-DAB converter.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.216-226
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• 2015

The neutral beam injection generate ultra-high temperature energy in the tokamak of nuclear fusion. The neutral beam injection make up arc power supply, filament power supply and acceleration & deceleration power supply. The arc power supply has characteristics of low voltage and high current. Arc power supply generate arc through constant output of voltage and current. So this paper proposed suitable buck converter for low voltage and high current. The proposed buck converter used parallel switch because it can be increased capacity and decrease conduction loss. When an arc generated, the neutral beam injection chamber occur high voltage. And it will break output capacitor of buck converter. Therefore the output capacitor was removed in the proposed converter. Thus the proposed converter should be designed for the characteristics of low voltage and high current. Also, the arc power supply should be guaranteed for system stability. The proposed parallel buck converter enables the system stability of the divided low output voltage and high current. The proposed converter with constant output be the most important design of the output inductor. In this paper, designed arc power supply verified operation of system and stability through simulation and prototype. After it is applied to the 288[kW] arc power supply for neutral beam injection.

• Journal of Power Electronics
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• v.13 no.6
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• pp.928-938
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• 2013

This paper proposes a novel control method for a multi-output switched-resonant converter. Output voltage can be regulated against variations in the supply voltage and load by controlling the voltage of the resonant capacitor (pulse amplitude control). Precise control is possible when pulse amplitude control is combined with pulse number control. The converter is analyzed, and design considerations are explained by using examples. Control implementation is described and load regulation and ripples are analyzed by simulation and hardware results. The topology is modified to obtain an additional negative output without any additional hardware other than a diode. The analysis of such a triple output converter with two positive outputs and one negative output is conducted and confirmed. The topology and control scheme are scalable to any number of outputs.