• 제목/요약/키워드: Capacitor mismatch compensation

검색결과 4건 처리시간 0.017초

캐패시터 부정합 보정 기능을 가진 8비트 스위치-캐패시터 사이클릭 D/A 변환기 설계 (A Design of 8-bit Switched-Capacitor Cyclic DAC with Mismatch Compensation of Capacitors)

  • 양상혁;송지섭;김석기;이계신;이용민
    • 전기학회논문지
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    • 제60권2호
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    • pp.315-319
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    • 2011
  • A switched-capacitor cyclic DAC scheme with mismatch compensation of capacitors is designed. In cyclic DAC, a little error between two capacitors is accumulated every cycle. As a result, the accumulated error influences the final analog output which is wrong data. Therefore, a mismatch compensation technique was proposed and the error can be effectively reduced, which alleviates the matching requirement. In order to verify the operation of the proposed DAC, an 8-bit switched-capacitor cyclic DAC is designed through HSPICE simulation and implemented through magna 0.18um standard CMOS process.

오프셋 전압을 이용한 계통 연계형 3상 3레벨 T-type 태양광 PCS의 중성점 전압 불평형 보상 (Compensation of Unbalanced Neutral Voltage for Grid-Connected 3-Phase 3-Level T-type Photovoltaic PCS Using Offset Voltage)

  • 박관남;최익;최주엽;이영권
    • 한국태양에너지학회 논문집
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    • 제37권6호
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    • pp.1-12
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    • 2017
  • The DC link of Grid-Connected 3-Phase 3-Level T-type Photovoltaic PCS (PV-PCS) consists of two series connected capacitors for using their neutral voltage. The mismatch between two capacitor characteristics and transient states happened in load change cause the imbalance of neutral voltage. As a result, PV-PCS performance is degraded and the system becomes unstable. In this paper, a mathematical model for analyzing the imbalance of neutral voltage is derived and a compensation method using offset voltage is proposed, where offset voltage adjusts the applying time of P-type and N-type small vectors. The validity of the proposed methods is verified by simulation and experiment.

System-On-Glass를 위한 Poly-Si TFT 소 면적 DC-DC 변환회로 (An Area-Efficient DC-DC Converter with Poly-Si TFT for System-On-Glass)

  • 이균렬;김대준;유창식
    • 대한전자공학회논문지SD
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    • 제42권2호
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    • pp.1-8
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    • 2005
  • System-on-glass를 위해 poly-Si TFT로 면적이 작으면서도 리플전압을 최소화한 DC-DC 전압 변환회로를 개발하였다. 전압 변환회로는 전하 펌핑 회로, 문턱전압 변화를 보상한 비교기, 오실레이터, 버퍼, 다중 위상 클럭을 만들기 위한 지연 회로로 구성된다. 제안한 다중 위상 클럭킹을 적용함으로써 클럭 주파수 또는 필터링 캐패시터의 증가 없이도 낮은 출력 리플전압을 얻음으로써 DC-DC 변환기의 면적을 최소화 하였다. 제안한 DC-DC 변환회로를 제작하여 측정한 결과 $R_{out}=100k\Omega,\;C_{out}=100pF$, 그리고 $f_{clk}=1MHz$에서 Dickson 구조와 기존의 cross-coupled 구조에서의 리플전압은 각각 590mv와 215mv인 반면 4-위상 클럭킹을 적용한 구조에서는 123mV이다. 그리고 50mV의 리플전압을 가지기 위해 필요한 필터링 캐패시터의 크기는 $I_{out}=100uA$$f_{clk}=1MHz$에서 Dickson 구조와 기존의 cross-coupled 구조에서는 각각 1029pF와 575pF인 반면 4-위상과 6-위상 클럭킹을 적용한 구조에서는 단지 290pF와 157pF만이 각각 요구된다. 구조별 효율로는 Dickson 구조의 전하 펌프에서는 $59\%$, 기존의 cross-coupled 구조와 본 논문에서 제안한 4-위상을 적용한 cross-coupled 구조의 전하 펌프에서는 $65.7\%$$65.3\%$의 효율을 각각 가진다.

Direct Imaging of Polarization-induced Charge Distribution and Domain Switching using TEM

  • 오상호
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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    • pp.99-99
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    • 2013
  • In this talk, I will present two research works in progress, which are: i) mapping of piezoelectric polarization and associated charge density distribution in the heteroepitaxial InGaN/GaN multi-quantum well (MQW) structure of a light emitting diode (LED) by using inline electron holography and ii) in-situ observation of the polarization switching process of an ferroelectric Pb(Zr1-x,Tix)O3 (PZT) thin film capacitor under an applied electric field in transmission electron microscope (TEM). In the first part, I will show that strain as well as total charge density distributions can be mapped quantitatively across all the functional layers constituting a LED, including n-type GaN, InGaN/GaN MQWs, and p-type GaN with sub-nm spatial resolution (~0.8 nm) by using inline electron holography. The experimentally obtained strain maps were verified by comparison with finite element method simulations and confirmed that not only InGaN QWs (2.5 nm in thickness) but also GaN QBs (10 nm in thickness) in the MQW structure are strained complementary to accommodate the lattice misfit strain. Because of this complementary strain of GaN QBs, the strain gradient and also (piezoelectric) polarization gradient across the MQW changes more steeply than expected, resulting in more polarization charge density at the MQW interfaces than the typically expected value from the spontaneous polarization mismatch alone. By quantitative and comparative analysis of the total charge density map with the polarization charge map, we can clarify what extent of the polarization charges are compensated by the electrons supplied from the n-doped GaN QBs. Comparison with the simulated energy band diagrams with various screening parameters show that only 60% of the net polarization charges are compensated by the electrons from the GaN QBs, which results in the internal field of ~2.0 MV cm-1 across each pair of GaN/InGaN of the MQW structure. In the second part of my talk, I will present in-situ observations of the polarization switching process of a planar Ni/PZT/SrRuO3 capacitor using TEM. We observed the preferential, but asymmetric, nucleation and forward growth of switched c-domains at the PZT/electrode interfaces arising from the built-in electric field beneath each interface. The subsequent sideways growth was inhibited by the depolarization field due to the imperfect charge compensation at the counter electrode and preexisting a-domain walls, leading to asymmetric switching. It was found that the preexisting a-domains split into fine a- and c-domains constituting a $90^{\circ}$ stripe domain pattern during the $180^{\circ}$ polarization switching process, revealing that these domains also actively participated in the out-of-plane polarization switching. The real-time observations uncovered the origin of the switching asymmetry and further clarified the importance of charged domain walls and the interfaces with electrodes in the ferroelectric switching processes.

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