• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• Progress in Medical Physics
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• v.12 no.1
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• pp.51-58
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• 2001

Synchrotron radiation (SR) has several advantages over convetional x-rays, including its phase, collimation, and high flux. A synchrotron radiation beamline 5C1 at Pohang Light Source (PLS) was recently built for imaging applications. We have shown that a SR imaging system is useful in imaging microscopic structures. SR with broad-band energy spectrum were adjusted to an object by Si wafers and their energy were approximately ranging from 6 keV to 30 keV. SR were passed through an object and finally transformed into visible lights by CdWO$_4$ scintillator screen. The visible lights which were reflected at an angle of 90 degrees by gold plated mirror were detected by a CCD camera and the image data were acquired using image acquisition system. A high-resolution phantom, capacitor, adult tooth, child tooth, cancerous breast tissue, and mouse lumbar vertebra were imaged with SR imaging system. The Objects were rotated within the field of view of the CCD detector, and their projection image data were obtained at 250 steps over 180 degrees rotation. Image reconstructions were carried out in a PC by using IDLTM(Research systems, Inc., US) program. The spatial resolution of the images acquired by the SR imaging system was measured with a high-resolution chart manufactured for several micrometer resolution. The specimens were also imaged with conventional x-ray radiography system to compare the image quality of radiography obtained with the SR imaging system. The results showed more structural details and high contrast images with SR imaging system than conventional x-ray radiography system. The SR imaging system may have a potential for imaging in biological researches, material applications, and clinical radiography.

• Applied Chemistry for Engineering
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• v.17 no.3
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• pp.243-249
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• 2006

Porous polymer gel electrolytes (PGEs) based on poly(vinylidenefluoride-co-hexafluoropropylene) (P(VdF-co-HFP)) as a polymer matrix and polyvinylpyrolidone (PVP) as a pore-forming agent were prepared and electrochemical properties were investigated for an electric double layer capacitor (EDLC) in order to increase a permeability of an electrolyte into the PGE. Propylene carbonate (PC) and ethylene carbonate (EC) as plasticizers, and tetraethylammonium tetrafluoroborate ($TEABF_4$) as a supporting salt for the PGE were used. EDLC unit cells were assembled with the PGE and electrode comprising BP-20 and MSP-20 as activated carbon powders, Super P as a conducting agent, and P(VdF-co-HFP)/PVP as a mixed binder. Ion conductivity of PGEs increased with an increased PVP content and was the best at 7 wt% PVP, whereas electrochemical characteristics such as AC-ESR of unit cell were better in 3 wt%. And electrochemical characteristics of the unit cell with PGE were the best at a 33 : 33 weight ratio of PC to EC. Specific capacitance of a mixed plasticizer system of PE and EC was higher than that of pure PC. Ion conductivity of PGEs with a film thickness of $20{\mu}m$ was higher, but electrochemical characteristics of unit cells were higher for a $50{\mu}m$ membrane thickness. Also, the unit cell has shown the highest capacitance of 31.41 F/g and more stable electrochemical performance when PGE and electrode were hot pressed. Consequently, the optimum composition ratio of PGE for EDLCs was 23 : 66 : 11 wt% such as P(VdF-co-HFP) : PVP = 20 : 3 wt% and PC : EC = 44 : 22 wt%. In this case, $3.17{\times}10^{-3}S/cm$ of ion conductivity was achieved at the $50{\mu}m$ thickness of PGE for EDLCs. And the electrochemical characteristics of unit cells were $2.69{\Omega}$ of DC-ESR, 28 F/g of specific capacitance, and 100% of coulombic efficiency.

• Korean Journal of Materials Research
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• v.5 no.6
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• pp.754-762
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• 1995

Strontium titanate(SrTiO$_3$) thin film was prepared on Si substrates by RF magnetron sputtering for a high capacitance density required for the next generation of LSTs. The optimum deposition conditions for SrTiO$_3$thin film were investigated by controlling the deposition parameters. The crystallinity of films and the interface reactions between SrTO$_3$film and Si substrate were characterized by XRD and AES respectively. High quality films were obtained by using the mixed gas of Ar and $O_2$for sputtering. The films were deposited at various bias voltages to obtain the optimum conditions for a high quality file. The best crystallinity was obtained at film thickness of 300nm with the sputtering gas of Ar+20% $O_2$and the bias voltage of 100V. The barrier layer of Pt(100nm)/Ti(50nm) was very effective in avoiding the formation of SiO$_2$layer at the interface between SrTiO$_3$film and Si substrate. The capacitor with Au/SrTiO$_3$/Pt/Ti/SiO$_2$/Si structure was prepared to measure the electric and the dielectric properties. The highest capacitance and the lowest leakage current density were obtained by annealing at $600^{\circ}C$ for 2hrs. The typical specific capacitance was 6.4fF/$\textrm{cm}^2$, the relative dielectric constant was 217, and the leakage current density was about 2.0$\times$10$^{-8}$ A/$\textrm{cm}^2$ at the SrTiO$_3$film with the thickness of 300nm.

• The Journal of Engineering Geology
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• v.31 no.3
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• pp.433-445
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• 2021

Plasma blasting by high voltage arc discharge were performed in laboratory-scale soil samples to investigate the fluid penetration efficiency. A plasma blasting device with a large-capacity capacitor and columnar soil samples with a diameter of 80 cm and a height of 60 cm were prepared. Columnar soil samples consist of seven A-samples mixed with sand and silt by ratio of 7:3 and three B-samples by ratio of 9:1. When fluid was injected into A-sample by pressure without plasma blasting, fluid penetrated into soil only near around the borehole, and penetration area ratio was less than 5%. Fluid was injected by plasma blasting with three different discharge energies of 1 kJ, 4 kJ and 9 kJ. When plasma blasting was performed once in the A-samples, penetration area ratios of the fluid were 16-25%. Penetration area ratios were 30-48% when blastings were executed five times consecutively. The largest penetration area by plasma blasting was 9.6 times larger than that by fluid injection by pressure. This indicates that the higher discharge energy of plasma blasting and the more numbers of blasting are, the larger are fluid penetration areas. When five consecutive plasma blasting were carried out in B-sample, fluid penetration area ratios were 33-59%. Penetration areas into B-samples were 1.1-1.4 times larger than those in A-samples when test conditions were the same, indicating that the higher permeability of soil is, the larger is fluid penetration area. The fluid penetration radius was calculated to figure out fluid penetration volume. When the fluid was injected by pressure, the penetration radius was 9 cm. Whereas, the penetration radius was 27-30 cm when blasting were performed 5 times with energy of 9 kJ. The radius increased up to 333% by plasma blasting. All these results indicate that cleaning agent penetrates further and remediation efficiency of contaminated soil will be improved if plasma blasting technology is applied to in situ cleaning of contaminated soil with low permeability.

• Korean Chemical Engineering Research
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• v.60 no.1
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• pp.86-92
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• 2022

Recently, the bio-healthcare market is enlarging worldwide due to various reasons such as the COVID-19 pandemic. Among them, biometric measurement and analysis technology are expected to bring about future technological innovation and socio-economic ripple effect. Existing systems require a large-capacity battery to drive signal processing, wireless transmission part, and an operating system in the process. However, due to the limitation of the battery capacity, it causes a spatio-temporal limitation on the use of the device. This limitation can act as a cause for the disconnection of data required for the user's health care monitoring, so it is one of the major obstacles of the health care device. In this study, we report the concept of a standalone healthcare monitoring module, which is based on both triboelectric effects and electromagnetic effects, by converting biomechanical energy into suitable electric energy. The proposed system can be operated independently without an external power source. In particular, the wireless foot pressure measurement monitoring system, which is rationally designed triboelectric sensor (TES), can recognize the user's walking habits through foot pressure measurement. By applying the triboelectric effects to the contact-separation behavior that occurs during walking, an effective foot pressure sensor was made, the performance of the sensor was verified through an electrical output signal according to the pressure, and its dynamic behavior is measured through a signal processing circuit using a capacitor. In addition, the biomechanical energy dissipated during walking is harvested as electrical energy by using the electromagnetic induction effect to be used as a power source for wireless transmission and signal processing. Therefore, the proposed system has a great potential to reduce the inconvenience of charging caused by limited battery capacity and to overcome the problem of data disconnection.