• The Transactions of the Korea Information Processing Society
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• v.7 no.6
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• pp.1746-1752
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• 2000

In this paper, a cache mechanism is proposed to improve the speed of query processing in distributed director database systems. To decrease search time of requested objects and query processing time. query requests and results about objects in a remote site are stored in the cache of a local site. Cache system architecture is designed according to the classified information. Cache schema are designed for each cache information. Operational algorithms are developed for meta data cache which has meta data tree. This tree improves the speed of query processing by reducing the scope of search space. Finally, performance evaluation is performed by comparing the proposed cache mechanism with X500.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.2
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• pp.205-214
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• 1997

In this paper, we suggest a cache mechanism to improve the speed fo query processing in distributed directory environment. For this, request and result and result about objects in remote site are store in the cache of local site. A cache mechanism developed through six phases; 1) Cached information which stored in distributed directory system is classified as application data, system data and meta data. 2) Cache system architecture is designed according to classified information. 3) Cache schema are designed for each cache information. 4) Least-TTL algorithms which use the weighted value of geograpical information and access frquency for replacements are developed for datacaches(application cache, system cache). 5) Operational algorithms are developed for meta data cache which has meta data tree. This tree is based on the information of past queries and improves the speed ofquery processing by reducing the scope of search space. 6) Finally, performance evaluations are performed by comparing with proposed cache mechanism and other mechanisms.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.12
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• pp.6123-6138
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• 2018

Named data networking (NDN) is a new network architecture designed for next generation Internet. Router-side content caching is one of the key features in NDN, which can reduce redundant transmission, accelerate content distribution and alleviate congestion. However, several security problems are introduced as well. One important security risk is cache privacy leakage. By measuring the content retrieve time, adversary can infer its neighbor users' hobby for privacy content. Focusing on this problem, we propose a cache privacy protection mechanism (named as CPPM-DAM) to identify legitimate user and adversary using Bloom filter. An optimization for storage cost is further provided to make this mechanism more practical. The simulation results of ndnSIM show that CPPM-DAM can effectively protect cache privacy.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.10 no.2
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• pp.74-79
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• 2011

The goal of this research is to reduce dynamic and static power consumption for a low power cache system. The proposed cache can achieve a low power consumption by using a drowsy and a way prediction mechanism. For reducing the static power, the drowsy technique is used at 4-way set associative cache. And for reducing the dynamic energy, one among four ways is selectively accessed on the basis of information in the Way-Line Prediction Unit (WLPU). This prediction mechanism does not introduce any additional delay though prediction misses are occurred. The WLPU can effectively reduce the performance overhead of the conventional drowsy caching by waking only a drowsy cache line and one way in advance. Our results show that the proposed cache can reduce the power consumption by about 40% compared with the 4-way drowsy cache.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.17-26
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• 2008

This paper proposes an efficient caching mechanism appropriate for the integrated RFID middleware which can integrate wireless sensor networks (WSNs) and RFID (radio frequency identification) systems. The operating environment of the integrated RFID middleware is expected to face the situations of a significant amount of data reading from RFID readers, constant stream data input from large numbers of autonomous sensor nodes, and queries from various applications to history data sensed before and stored in distributed storages. Consequently, an efficient middleware layer equipping with caching mechanism is inevitably necessary for low latency of request-response while processing both data stream from sensor networks and history data from distributed database. For this purpose, the proposed caching mechanism includes two optimization methods to reduce the overhead of data processing in RFID middleware based on the classical cache implementation polices. One is data stream cache (DSC) and the other is history data cache (HDC), according to the structure of data request. We conduct a number of simulation experiments under different parameters and the results show that the proposed caching mechanism contributes considerably to fast request-response times.

• Smart Media Journal
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• v.4 no.2
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• pp.62-67
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• 2015

During several decades, hard disk drive(HDD) has been used in most computer systems as secondary storage and, however, the performance enhancement of HDD is limited by its mechanical properties. On the other hand, although the flash memory based solid state drive (SSD) has more advantages over HDD such as high performance and low noise, SSD is still too expensive for common usage and expected to take several years to replace HDD completely. Therefore, SSD caching mechanism using the SSD as a cache of high capacity HDD has been highlighted lately. The representatives of SSD caching mechanisms are typically bcache, dm-cache, Flashcache, and EnhanceIO. Each of them has its own internal mechanism and implementation, and this makes them to show their own pros. and cons. In this paper, we analyze the characteristics of each SSD caching mechanisms and compare the performance of them under various workloads. We expect that our contribution will be useful to enhance the performance of SSD caching mechanisms.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.106-111
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• 2023

The importance of load-to-use latency has been highlighted as state-of-the-art computing cores adopt deep pipelines and high clock frequencies. The cascaded cache was recently proposed to reduce the access cycle of the L1 cache by utilizing differences in latencies among banks of the cache structure. However, this study assumes the cache is comprised of SRAM, making it unsuitable for direct application to non-volatile memory-based systems. This paper proposes a novel mechanism and structure for lowering dynamic energy consumption. It inserts monitoring logic to keep track of swap operations and write counts. If the ratio of swap operations to total write counts surpasses a set threshold, the cache controller skips the swap of cache blocks, which leads to reducing write operations. To validate this approach, experiments are conducted on the non-volatile memory-based cascaded cache. The results show a reduction in write operations by an average of 16.7% with a negligible increase in latencies.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.6
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• pp.1255-1261
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• 2020

Cache side-channel attack is a class of attacks to retrieve sensitive information from a system by exploiting shared cache resources in CPUs. As the attacks are delivered to wide range of environments from mobile systems to cloud systems recently, many detection strategies have been proposed. Since the conventional cache side-channel attacks are likely to incur tremendous number of cache events, most of the previous detection mechanisms were designed to carefully monitor mostly cache events. However, recently proposed attacks tend to incur less cache events during the attack. PRIME+ABORT attack, for example, leverages the Intel TSX instead of accessing cache to measure access time. Because of the characteristic, attack detection mechanisms based on cache events may hardly detect the attack. In this paper, we conduct an in-depth analysis of the PRIME+ABORT attack to identify the other useful hardware events for detection rather than cache events. Based on our finding, we present a novel mechanism called PRIME+ABORT Detector to detect the PRIME+ABORT attack and demonstrate that the detection mechanism can achieve 99.5% success rates with 0.3% performance overhead.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.3
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• pp.254-265
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• 2003

This paper presents the design and implementation of stream control mechanisms which are necessary for the development of an efficient streaming cache server. The streaming protocols used in our implementation are the RTSP/RTP/RTCP standards. The mechanisms support both the on-demand media caching and real-time media splitting applications. The core of the stream control includes the session management, which handles the RTSP/RTCP control session and the RTP transport session, and the cache block management which efficiently manages the RTP-based cache blocks stored in the cache server. The streaming cache server with the proposed stream control mechanism has successfully been implemented on a Linux platform and it works well with the Apple's QTSS server and the QuickTime player for both on-demand and splitting media services.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1084-1089
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• 2004

This paper describes the improvement of web cache server by scoping in replacement algorithm of data which are collected from the clients. We have found that each replacement algorithm is suitable for each type of data in the web pages. Therefore, we introduce the mechanism to select the replacement algorithm depending on the size of data called the Replacement Algorithm Selection Mechanism (RASM). RASM allows the web cache server to have the suitable replacement algorithm for each type of data. As the result, the byte hit ratio of web cache server can be increased and the congestion in the network can be alleviated.