• Journal of Digital Convergence
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• v.17 no.9
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• pp.153-161
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• 2019

Discrimination of media object segments in wireless home proxies has a significant impact on caching delay, and caching delay degrades the performance of the proxy. In this paper, we propose a Single Fetching Smart Caching (SFSC) strategy and a Multi-Fetching Smart Caching (MFSC) strategy to improve the proxy performance of the home network and improve the caching performance for media object segments. The SFSC strategy is a technique that performs caching by sequential fetching of object segments requested by the home node one at a time, which guarantees a faster cache hit rate, and the MFSC strategy is a technique that caches the media object segments by blocking object segments requested by the home node one at a time, which improves the throughput of cache. Simulation results show that the cache hit rate and the caching delay are more efficient than the MFSC technique, and the throughput of the object segment is more efficient than that of the SFSC technique.

• Journal of Digital Contents Society
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• v.11 no.1
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• pp.91-97
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• 2010

Flash memory has been used by many digital devices for data storage, exploiting the advantages of non-volatility, low power, stability, and so on, with the help of high integrity, large capacity, and low price. As the fast growing popularity of flash memory, the density of it increases so significantly that its entire address mapping table becomes too big to be stored in SRAM. This paper proposes the associated page address cache with an efficient table management scheme for hybrid flash translation layer mapping. For this purpose, all tables are integrated into a map block containing entire physical page tables. Simulation results show that the proposed scheme can save the extra memory areas and decrease the searching time with less 2.5% of miss ratio on PC workload and can decrease the write overhead by performing write operation 33% out of total writes requested.

• ETRI Journal
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• v.10 no.3
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• pp.49-61
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• 1988

HARP(High-performance Architecture for Risc-type Processor)는 한국전자통신연구소에서 정의한 고유모델의 RISC형 32비트 CPU이다. HACAM(HArp CAche and Mmu)은 HARP의 캐쉬 메모리 및 MMU(Memory Management Unit)를 custom IC로 구현한 VLSI 칩이다. 본 논문에서는 HACAM의 구조 설계에 대해 메모리 구조 및 메모리 관리 방식, 캐쉬 메모리 및 HACAM의 구성 등으로 나누어 설명하고 그 타당성을 논하였다.

• Journal of Korea Multimedia Society
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• v.21 no.8
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• pp.942-951
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• 2018

In these days, 360 degree videos, which is provided via VR, have high resolution and quality of 8K. These kinds of videos inevitably require streaming technology which guarantees QoS. Therefore, we suggest MPEG DASH HTTP protocol which stably provides streaming services of high quality videos in 8K, which are 360 degree tile-encoded, on low-spec devices such as OTT and IPTV Settop and Tile Segment Cache management structure for servers operating streaming services.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.235-238
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• 2002

This paper proposes a novel scheme of designating non-cacheable addresses of memories in embedded systems of multi-master architectures without a Memory Management Unit (MMU). As a solution for data coherency problem between external memories and a cache memory, we proposes a cache masking scheme by allocating the most significant bit of address not used in 32-bit address system as indicator bit to designate non-cacheable address. As this scheme enables non-cacheable area designation every address, the simpler in the aspect of hardware and more flexible size of non-cacheable area can be obtained.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.167-170
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• 2001

본 논문에서는 미국에서 고 선명(High Definition) TV를 위한 오디오 표준인 ATSC에 의해서 채택되고, DVD의 오디오 코덱으로 널리 채택된 Dolby AC-3 복호화기를 고정 소수점으로 변환한 후, ARM929T를 기반으로 실시간 구현하였다. 실시간 구현에 사용된 ARM920T 는 저전력 소비형 32-비트 고정 소수점 RISC 구조이며, 명령어 Cache 와 데이터 Cache, MMU(Memory Management Unit)로 구성되어 있다. 그리고 200MIPS 의 성능을 가지고 있어, 음성/오디오, 통신, 디지털 셀룰라폰에 적용할 수 있고, ASIC 화 할 수 있는 장점을 가지고 있다. 구현된 AC-3 복호화기는 약 67MIPS(6 채널, 640kbps, 48KHz)의 복잡도를 나타내며, 사용된 메모리양은 프로그램 ROM 23.3K Bytes, 데이터 ROM(table) 4.62K Bytes 및 RAM 45K Bytes 이다. 구현된 AC-3 복호화기는 Dolby사에서 제공하는 40 개의 test 벡터들을 bit-exact하게 통과하였다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.07a
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• pp.235-236
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• 2014

플래시 메모리 기술이 발전함에 따라 낸드 플래시 기반의 SSD가 상용화 되면서 I/O시간을 줄이기 위한 연구들이 진행되고 있다. 이에 본 논문에서는 기존의 메인 메모리와 저장장치 사이에 확장 버퍼 캐시로써 SSD를 사용하고 메인 메모리에서 방출 된 페이지들을 구분하여 같은 성향의 페이지들을 블록화 하는 모델을 제안한다. 이러한 모델을 통하여 블록 단위로 사용되는 SSD를 효율적으로 이용하여 읽기 및 쓰기 성능을 높이고 I/O에 해당하는 시간들을 줄임으로써 전체적인 성능 향상을 증명하였다.

• Journal of the Korea Society of Computer and Information
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• v.8 no.3
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• pp.40-46
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• 2003

The high-performance processors have recently employed sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. For the query processing of database management systems, those hardware characteristics are the important research issue. The latest works show that the cache miss penalty between main memory and CPU becomes new bottlenecks and the branch misprediction causes serious resource-waste. An effcient algorithm for query processing of aggregate functions considering these hardware characteristics was proposed in this dissertation.

• The Transactions of the Korea Information Processing Society
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• v.6 no.12
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• pp.3642-3651
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• 1999

In this paper, we propose a new caching scheme for continuous media data where the buffer allocation unit is divided into two modes : interval and object. All of objects' access patterns are monitored and based on the results of monitoring, a request for an object is decided to cache its data with either interval mode or object mode. The results of our simulation show that our proposed caching scheme is better than the existing caching algorithms such as interval caching where the access patterns of the objects are changed with time.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.1379-1382
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• 2004

The use of a cache for storing and processing of Web objects is becoming larger. Also, many studies on the efficient management of the storing scope of caches are being done. Web caching algorithms have many differences from traditional algorithms. Particularly, heterogeneity of Web objects that are processing units of Web caching, and a variation of Web object reference characteristic with time are the important causes of the decrease the performance of existing algorithms. In this study, we proposed the new web-caching algorithm. A heterogeneity variation of an object can be reduced as the proposed method dividedly managing Web objects and a cache scope with heterogeneity, and it is adaptively reflecting a variation of object reference characteristics with the flowing of time. In the experiments, we verified that the performance of the proposed method was more improved than existing algorithms through the two experiment models which considered heterogeneity of an object.