• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.70.3-70
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• 2001

In this paper, we suggest a kernel level multi thread web accelerator (called the SCALA-AX), which significantly improves the performance of the web soerver. In comparison with a conventional proxy web cache that is generally called a caching server and a simple content-copy based system, the primary functions and goals of SCALA-AX are designed to maximize the content services of a front end web server with high performance. Specifically, the SCALA-AX runs on the kernel level of a web sorrel, based on the newest caching techniques. Moreover, the SCALA-AX supports the http 1.1 protocol and allows the dynamic pages as well as static pages to be processed.

• ETRI Journal
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• v.41 no.3
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• pp.348-357
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• 2019

Fog radio access network (F-RAN) architectures provide markedly improved performance compared to conventional approaches. In this paper, an efficient genetic algorithm-based content distribution scheme is proposed that improves the throughput and reduces the transmission delay of a F-RAN. First, an F-RAN system model is presented that includes a certain number of randomly distributed fog access points (F-APs) that cache popular content from cloud and other sources. Second, the problem of efficient content distribution in F-RANs is described. Third, the details of the proposed optimal genetic algorithm-based content distribution scheme are presented. Finally, simulation results are presented that show the performance of the proposed algorithm rapidly approaches the optimal throughput. When compared with the performance of existing random and exhaustive algorithms, that of the proposed method is demonstrably superior.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.11a
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• pp.655-658
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• 2007

It is difficult to provide a video on demand (VoD) service to a large number of users via the Internet. This is due to the characteristics of VoD, which require a large bandwidth for a long playing time. The Peer-to-Peer (P2P) concept is proposed to increase the scalability of the VoD service. Many studies have been undertaken to solve this problem. But its success is still quite limited technically, these research have been deployed in a rush, mostly based on practicality and instability. A system which uses a distributed VoD streaming scheme over P2P network is proposed to support media streaming.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.765-768
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• 2007

P2P Video-on-Demand (VoD) is becoming a popular service in the Internet. The first deployments are already in place, and millions of customers worldwide are already using this new medium. But its success is still quite limited and technically, these researches have been deployed in a rush, mostly based on practicality and instability. This paper studies the advantages and potential problems of VoD in peer-to-peer (P2P) network, we propose a system which uses a distributed VoD streaming scheme over P2P network to support media streaming.

• ETRI Journal
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• v.42 no.4
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• pp.468-479
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• 2020

The proposed AI processor architecture has high throughput for accelerating the neural network and reduces the external memory bandwidth required for processing the neural network. For achieving high throughput, the proposed super thread core (STC) includes 128 × 128 nano cores operating at the clock frequency of 1.2 GHz. The function-safe architecture is proposed for a fault-tolerance system such as an electronics system for autonomous cars. The general-purpose processor (GPP) core is integrated with STC for controlling the STC and processing the AI algorithm. It has a self-recovering cache and dynamic lockstep function. The function-safe design has proved the fault performance has ASIL D of ISO26262 standard fault tolerance levels. Therefore, the entire AI processor is fabricated via the 28-nm CMOS process as a prototype chip. Its peak computing performance is 40 TFLOPS at 1.2 GHz with the supply voltage of 1.1 V. The measured energy efficiency is 1.3 TOPS/W. A GPP for control with a function-safe design can have ISO26262 ASIL-D with the single-point fault-tolerance rate of 99.64%.

• Journal of the Korea Computer Industry Society
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• v.2 no.12
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• pp.1533-1540
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• 2001

In this paper, we described extraction method of electrical parameters and modeling method of PCB nets on PCB design process. To analyze electrical characteristics of real PCB structure, we selected a cache memory system as an experimental board and designed 6 layer PCB substrate. For extraction of the electrical parameters, we divided circuit elements into the components of conductor types which are wires, via holes, BGA balls etc. and combined the calculated value by real net structure to modeling the PCB nets. We analyzed the electrical characteristics of the PCB nets with the simulation tools of SPICE and XNS. The simulation analysis has shown that the maximum signal delay was 2.6ns and the maximum crosstalk noise was 281 mV and we found that the designed substrate was adequate to system specification.

• International Journal of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.6-11
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• 2018

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation.These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.149-155
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• 2007

In this paper, we propose an real-time implementation of JPEG2000 codec on the ARM9 processor. The implemented codec is designed to separate control codes from data management codes in order to use effectively the system resources such as processor and memory. Especially, in embedded situations like cellular phones it is very important to provide good services using limited processor and internal memory. Since ARM9 series processors do not provide floating-point, large amount of computational time is required to perform the operation which needs highly repetitive floating-point computations like DWT(discrete wavelet transform). The proposed codec was programed using fixed-point to overcome this weakness. Also code optimization considering cache memory was applied to further improve the computational speed.

• The Transactions of the Korea Information Processing Society
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• v.7 no.3
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• pp.776-787
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• 2000

Write requests which stored in disk cache of the RAID5 controller should be destaged to disk arrays according to the destage algorithm. As the response performance of the parallel IO request is being hit by the effect of the destage, several destage algorithms have been studied to enhance the performance of he RAID5 controller. Among the destage algorithms, the load balancing destage algorithm has better performance than other destage algorithms when system load is highly increased. But the load balancing destage algorithm gives priority to load balance among the disks in disk arrays, therefore, when some disks are affected by the very heavy system load caused by small data requests, the load balancing destage algorithm cannot enhance the performance of parallel IO requests effectively since it makes effort to maintain the load balance without the benefit of the locality of the write requests. This paper proposes a new RAID5 controller that applied reference-load balancing destage algorithm which decides the destage priority based on the reference history and load distribution of the disks. The simulation results show that RAID5 controller with the reference-load balancing destage algorithm has better performance than previous load balancing destage algorithm.

• The KIPS Transactions:PartC
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• v.12C no.2 s.98
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• pp.243-250
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• 2005

To introduce the cache in a client is one of the methods to migrate the performance degradation of broadcast systems doe to the inherent restrictions of wireless communication environments such as low bandwidth or frequent disconnections. In this paper, we propose a pull-based broadcast strategy in hybrid-based data broadcast systems using bit vectors in order to effectively broadcast data recently requested by clients. Then, we propose a caching strategy considering the characteristics of data broadcast algorithm and then evaluate the performance of the system. According to the result of evaluation, the system employing the proposed strategies shows the better performance in terms of response time.