• The KIPS Transactions:PartA
• /
• v.13A no.3 s.100
• /
• pp.191-198
• /
• 2006

Today's portable electric consumer devices, which are operated by battery, tend to integrate more multimedia processing capabilities. In the multimedia processing devices, multimedia system-on-chips can handle specific algorithms which need intensive processing capabilities and significant power consumption. As a result, the power-efficiency of multimedia processing devices becomes important increasingly. In this paper, we propose a reconfigurable data caching architecture, in which data allocation is constrained by software support, and evaluate its performance and power efficiency. Comparing with conventional cache architectures, power consumption can be reduced significantly, while miss rate of the proposed architecture is very similar to that of the conventional caches. The reduction of power consumption for the reconfigurable data cache architecture shows 33.2%, 53.3%, and 70.4%, when compared with direct-mapped, 2-way, and 4-way caches respectively.

• Journal of KIISE:Databases
• /
• v.30 no.4
• /
• pp.408-419
• /
• 2003

Data warehouses are usually dedicated to the processing of quires issued by decision support system(DSS). The response time of DSS queries is typically several orders of magnitude higher than the one of OLTP queries. Since DSS queries are often submitted interactively, techniques for reducing their response time are important. The caching of query results is one such technique particularly well suited to the DSS environment. In this paper, we present a cache manager for such an environment. Specifically, we define a canonical form of query. The cache manager looks up a query based on the exact query match or using a suggested query split process if the query is found is non-canonical form or in canonical form, respectively. It dynamically maintains the cache content by employing a profit function which reflects in an integrated manner the query execution cost, the size of query result, the reference rate, the maintenance cost of each result due to updates of their base tables, and the frequency of such updates. We performed the experimental evaluation and it positively shows the performance benefit of our cache manager.

• The KIPS Transactions:PartC
• /
• v.9C no.2
• /
• pp.181-188
• /
• 2002

There are recently a lot of inconvenience because every client should be set to the proxy server on the browser in order to control the access by means of the client authentication in the proxy server. The client authentication technology using the transparency cache in this paper will be transparently used for every user in the internet which option of the authentication function is simply set in the cache server. In addition, the administrator will get the benefit since he can control the traffic of each client and strengthen the security. And also, this system is expected to use in the eCRM deeply rotated to the tendency of the client in the field of the e-commerce like shopping mall in the internet since the administrator can monitor the pattern of the client using the internet. This technique can be applied to the company affiliated research center, the EC website, and the military where it is essential for the tight security even though there are no additional security devices.

• KIPS Transactions on Computer and Communication Systems
• /
• v.12 no.1
• /
• pp.1-8
• /
• 2023

It is impossible to overwrite on an already allocated page in SSDs, so whenever a write operation occurs a page replacement with a clean page is required. To resolve this problem, SSDs have an internal flash translation layer called FTL that maps logical pages managed by a file system of operating system to currently allocated physical pages. SSD pages discarded due to write operations must be recycled through initialization, but since the number of initialization times is limited the FTL provides a caching function to reduce the number of writes in addition to the page mapping function, which is a core function. In this study, we focus on the FTL cache methodologies reducing the number of page writes and analyze the related algorithms, and propose a write-only cache strategy. As a result of experimenting with the write-only cache using a simulator, it showed an improvement of up to 29%.

• The Journal of the Acoustical Society of Korea
• /
• v.20 no.6
• /
• pp.46-50
• /
• 2001

This paper proposes a new recognition time reduction algorithm Score-Cache technique, which is applicable to the HMM-base speech recognition system. Score-Cache is a very unique technique that has no other performance degradation and still reduces a lot of search time. Other search reduction techniques have trade-offs with the recognition rate. This technique can be applied to the continuous speech recognition system as well as the isolated word speech recognition system. W9 can get high degree of recognition time reduction by only replacing the score calculating function, not changing my architecture of the system. This technique also can be used with other recognition time reduction algorithms which give more time reduction. We could get 54% of time reduction at best.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.6
• /
• pp.1390-1403
• /
• 1998

Database sharing system (DSS) refers to a system for high performance transaction processing. In DSS, the processing nodes are locally coupled via a high speed network and share a common database at the disk level. Each node has a local memory, a separate copy of operating system, and a DB'\fS. To reduce the number of disk accesses, the node caches database pages in its local memory buffer. However, since multiple nodes may be simultaneously cached a page, cache consistency must be cnsured so that every node can always access the'latest version of pages. In this paper, we propose efficient cache consistency schemes in DSS, where the database is logically partitioned using primary copy authority to reduce locking overhead, The proposed schemes can improve performance by reducing the disk access overhead and the message overhead due to maintaining cache consistency, Furthermore, they can show good performance when database workloads are varied dynamically.

• Journal of the Korea Society of Computer and Information
• /
• v.12 no.6
• /
• pp.139-146
• /
• 2007

A hard disk. which can be classified as an external storage is usually capacious and economical. In spite of the attractive characteristics and efforts on the performance improvement, however, the operation of the hard disk is apparently slower than a processor and the advancement has also been slowly conducted since it is based on mechanical process. On the other hand. the advancement of the processor has been drastically performed as semiconductor technology does. So, disk I/O sub-system becomes bottleneck of computer systems' performance. For this reason. the research on disk I/O sub-system is in progress to improve computer systems' performance. In this paper, we proposed multi-level LRU scheme and then apply it to the computer systems with buffer cache and disk cache. By applying the proposed scheme to computer systems. the average access time to ask blocks can be decreased. The efficiency of the proposed algorithm was verified by simulation results.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.30 no.7
• /
• pp.68-80
• /
• 2002

An approach for composing a performance optimized computational code is suggested for latest microprocessors. The concept of the code optimization, called here as localization, is maximizing the utilization of the second level cache that is common to all the latest computer system, and minimizing the access to system main memory. In this study, the localized optimization of LU-SGS (Lower-Upper Symmetric Gauss-Seidel) code for the solution of fluid dynamic equations was carried out in three different levels and tested for several different microprocessor architectures most widely used in these days. The test results of localized optimization showed a remarkable performance gain up to 7.35 times faster solution, depending on the system, than the baseline algorithm for producing exactly the same solution on the same computer system.

• The KIPS Transactions:PartA
• /
• v.12A no.3 s.93
• /
• pp.215-222
• /
• 2005

The efficient utilization of cache memories is a key factor in achieving high performance for computing large signal transforms. Nonunit stride access in computation of large DFTs causes cache conflict misses, thereby resulting in poor cache performance. It leads to a severe degradation in overall performance. In this paper, we propose a dynamic data layout approach considering the memory hierarchy system. In our approach, data reorganization is performed between computation stages to reduce the number of cache misses. Also, we develop an efficient search algorithm to determine the optimal tree with the minimum execution time among possible factorization trees considering the size of DFTs and the data access stride. Our approach is applied to compute the fast Fourier Transform (FFT). Experiments were performed on Pentium 4, $Athlon^{TM}$ 64, Alpha 21264, UtraSPARC III. Experiment results show that our FFT achieve performance improvement of up to 3.37 times better than the previous FFT packages.

• Journal of KIISE:Information Networking
• /
• v.27 no.2
• /
• pp.149-159
• /
• 2000

In mobile computing environments, invalidation and propagation method based on broadcasting is used to transmit the information for cache maintenance of mobile hosts. Previous researches generally adopted invalidation method that easily adapts to the limited network bandwidth and the frequent disconnection. But the invalidation of frequently accessed data causes the contention on the wireless network with the increasing cache requests. Although the propagation method can reduce the cache requests, the high probability of broken message or loss of message is the main factor that degrades the system performance. To resolve these problems, we propose adaptive cache maintenance scheme that dynamically adjusts the broadcasting ratio of invalidation and propagation, according to the wireless network connection states. The proposed scheme broadcasts the propagation message in stable connection state, so it can reduce the cache requests and server response time. With the decreasing available network bandwidth by the frequent partial disconnection and disconnection, the proposed scheme dynamically increases the broadcasting ratio of the invalidation messages to minimize the broken message or the loss of message probability. Consequently, the proposed scheme resolves the problems which arise in the invalidation or propagation method in mobile computing environments.