• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.128-130
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• 2007

The research degined model which was integrated Cache technical for improvement of modebus protocol. The mode bus it leads and it does not solve in existing to shorten the tank data computing time. It desigine the algorithm which discriminates the shift time of the petrochemistry process tank m following. It is an objective of dissertation.

• The Transactions of the Korea Information Processing Society
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• v.7 no.12
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• pp.3964-3975
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• 2000

There are two policies for maintaining consistency among the multiple processor caches in a multiprocessor system: Write invalidate and Write update. In the write invalidate policy, whenever a processor attempt to write its cached block, it has to invalidate all the same copies of the updated block in the system. As a results of this frequent invalidations, this policy results in high cache miss ratio. On the other hand, the write update policy renew them, instead of invalidating all the same copies. This policy has to transfer the updated contents through interconnection network, whether the updated block is ptivate or not. Therefore the network suffer from heavy transaction traffic. In this paper we present an efficient cache coherence protocol for shared memory multiprocessor system connected by slotted ring. This protocol is based on the write update policy, but the updated contents are transferred only in case of updating the shared block. Otherwise, if the updated block is private, the updated contents are not transferred. We analyze the proposed protocol and enforce simulation to compare it with previous version.

• The Journal of the Korea Contents Association
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• v.10 no.3
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• pp.64-71
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• 2010

Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.

• Proceedings of the KIEE Conference
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• 1998.11b
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• pp.630-632
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• 1998

The basic user location strategies proposed in current PCS(Personal Communication Services) Network are two-level Database strategies. These Databases which exist in the Signalling network always maintain user's current location information, and it is used in call setup process to a mobile user. As the number of PCS users are increasing, this strategies yield some problem such as concentrating signalling traffic on the Database, increasing Call setup Delay, and so on. In this paper, we proposed RCP(Reverse Connection setup Protocol) model, which apply RVC(Reverse Virtual Call setup) algorithm to PCS reference model, and CRCP(Cache algorithm in RCP) model, which adopt Caching strategies in the RCP model. When Cache-miss occur, we found that CRCP model require less miss-penalty than PCS model. Also we show that proposed models are always likely to yield better performance in terms of reduced Location Tracking Delay time.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1694-1705
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• 1997

In the future mobile computing environment, it will be generalized that a mobile host with portable Laptop of Palmtop accesses to database through wireless communication channel. For solving the problems which are caused from low bandwidth of wireless communication, mobile hosts cache the datum used frequently on them. Thus the mobile hosts must always retain the cache consistency for the correctness of the cached datum. the cache consistency is mainly affected from the unrestricted host mobility and the disconnection of the communication between mobile hosts and mobile support station. In this situation, the strategy to retain efficiently cache consistency is required. In this paper, we propose a strategy using updatable message for retaining the cache consistency, in the mobile computing environment, with replicated database supporting 2 phase commit protocol. This strategy makes use of a updatable message to resolve the cache consistency problem, since mobile host crosses the boundary of cell. In using of this updatable, it find out and cache only the update data of missing invalidation message. As a result, the proposed strategy utilizes network bandwidth efficiently because it is not need to delete all the cached datum with any datum change.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1990.06a
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• pp.832-836
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• 1990

• Journal of Communications and Networks
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• v.14 no.1
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• pp.91-103
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• 2012

Network mobility (NEMO) based on mobile IP version 6 has been proposed for networks that move as a whole. Route optimization is one of the most important topics in the field of NEMO. The current NEMO basic support protocol defines only the basic working mode for NEMO, and the route optimization problem is not mentioned. Some optimization schemes have been proposed in recent years, but they have limitations. A new NEMO route optimization scheme-involving a combination of the optimized route cache protocol (ORC) and reverse routing header (RRH) and the use of a quota mechanism for optimized sessions (OwR)-is proposed. This scheme focuses on balanced performance in different aspects. It combines the ORC and RRH schemes, and some improvements are made in the session selection mechanism to avoid blindness during route optimization. Simulation results for OwR show great similarity with those for ORC and RRH. Generally speaking, the OwR's performance is at least as good as that of the RRH, and besides, the OwR scheme is capable of setting up optimal routing for a certain number of sessions, so the performance can be improved and the cost of optimal routing in nested NEMO can be decreased.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1327-1330
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• 2003

The internet SCSI(iSCSI) disk has been studied as a storage system which can be directly connected to TCP/IP network. We designed and implemented a shared disk following the iSCSI protocol and providing cache consistency. It is named as intelligent iSCSI(i$^2$SCSI) disk. The i$^2$SCSI disk provides cache consistency of all blocks that belong to the disk using a conventional lease method and it uses 'contiguous blocks-level locking' The prototype of the i$^2$SCSI disk emulator and its client is designed and implemented in Linux 2.4.

• Electronics and Telecommunications Trends
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• v.13 no.5 s.53
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• pp.11-22
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• 1998

Recently, scalable multiprocessor systems are actively developed for general-purpose computing, which are based on distributed shared memory (DSM) architecture to boost up both programmability and scalability. In this paper, we survey and analyze cache coherence protocols in non-uniform memory access (NUMA) multiprocessor systems. In particular, it has been easily inferred that specialized hardware suitable for NUMA multiprocessor systems with commodity symmetric multiprocessors (SMPs) is highly required. The cache coherence protocol combined with specialized hardware can significantly improve the performance and scalability of NUMA multiprocessor systems, providing better programmability.

• Journal of Information Technology and Architecture
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• v.10 no.2
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• pp.159-167
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• 2013

Web Services offer many benefits over other types of middleware in distributed computing. However, usage of Web Services results in large network bandwidth since Web Services use XML-based protocol which is heavier than binary protocols. Even though there have been many researches to minimize the network traffic and bandwidth usages of Web Services messages, none of them are solving problem clearly yet. In this paper, we propose a transparent proxy with cache to avoid transfer of repeated SOAP data, sent by Web Service to an application. To maintain the cache consistency, we introduce publish/subscribe paradigm using WS-Eventing between the proxy and Web Service. The implemented system based on our proposed architecture will not compromise the standards of Web Service. The evaluation of our system shows that caching SOAP messages not only reduces the network traffic but also decreases the request delays.