• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1116-1118
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• 2005

We studied laser crystallization of amorphous silicon films prepared at ultra low temperatures ($<150^{\circ}C$). Amorphous silicon films having a low content of hydrogen were deposited by using catalytic chemical vapor deposition method. Influence of process parameters on the hydrogen content was investigated. Laser crystallization was performed dispensing with the preliminary dehydrogenation process. Crystallization took place at a laser energy density value as low as $70\;mJ/cm^2$, and the grain size increased with increasing the laser energy. The ELA crystallization of Catalytic CVD a-Si film is a promising candidate for Poly-Si TFT in active-matrix flexible display on plastic substrates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.1-4
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• 2011

This study was the coorrelation between the electrical properties and the dielectric constant of organic inorganic hybrid type low k SiOC film. SiOC film as low-k films was deposited by the chemical vapor deposition and then annealed at 30 $0{\sim}500^{\circ}C$ to find out the properties of the depending on the temperature and polarity. SiOC film decreased the dielectric constant after annealing process, and the electrical properties were improved at the sample annealed at $400^{\circ}C$. From the XRD patterns, there were two kinds of bonding structures in SiOC film. There was the difference in the bonding structure between the samples annealed under $300^{\circ}C$ and the samples annealed over $400^{\circ}C$. The change was confirmed near $400^{\circ}C$.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.15 no.6
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• pp.58-63
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• 2006

FIB equipment can perform sputtering and chemical vapor deposition simultaneously. It is very advantageously used to fabricate a micro structure part having 3D shape because the minimum beam size of ${\Phi}10nm$ and smaller is available. Since general FIB uses very short wavelength and extremely high energy, it can directly make a micro structure less than $1{\mu}m$. As a result, FIB has been probability in manufacturing high performance micro devices and high precision micro structures. Until now, FIB has been commonly used as a very powerful tool in the semiconductor industry. It is mainly used for mask repair, device correction, failure analysis, IC error correction, etc. In this paper FIB-Sputtering and FIB-CVD characteristic analysis were carried out according to $Ga^+$ ion beam current that is very important parameter for minimizing the pattern size and maximizing the yield. Also, for FIB-Sputtering burr caused by redeposition of the substrate characteristic analysis was carried out.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.274-274
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• 2010

최근 들어 나노선을 이용한 pn 접합 소자 연구 결과가 매우 활발하게 보고되고 있다. 그러나, 서로 다른 두 종류의 나노선으로 pn 접합 어레이 구조의 소자를 제작할 때, 나노선을 원하는 위치에 정렬하는 기술상의 어려움이 큰 걸림돌이 된다. 본 연구에서는 p-CNT와 n-$SnO_2$ 나노선을 이용한 pn 접합 어레이 구조를 제작할 수 있는 독창적인 공정기술을 제안한다. 먼저 $SiO_2$가 300 nm 성장된 Si 기판을 선택적으로 패터닝하여 BOE (6:1) 용액으로 $SiO_2$ 층을 80 nm 정도 선택적으로 에칭한 후, 선택적으로 에칭된 표면에 슬라이딩 장비를 이용하여 화학기상증착법(chemical vapor deposition: CVD)으로 성장된 n-$SnO_2$ 나노선을 전이시킨다. 그 다음 thermal tape를 이용하여 CVD 법으로 성장된 랜덤 네트워크 형태의 CNT를 $SnO_2$ 나노선이 전이된 기판 위에 전이 시킨다. 이때 성장된 CNT 필름 중 금속성 나노선을 통한 전하 이동을 감소시키기 위해, 촉매로 사용되는 페리틴의 농도를 낮춰서 전체적인 CNT의 농도를 줄이는 방법을 이용하였다. 따라서, 성장된 CNT 필름은 별도의 후처리 없이 p-형의 반도체성을 보였다. 제작된 pn-소자는 정류비가 ~103 인 정류특성을 보였으며, 254 nm 파장의 UV lamp를 조사하여 광전류가 발생하는 것을 확인하였다. 연구결과는 이종의 나노선 접합에 의한 다이오드 응용과 UV 센서응용 가능성을 보여준다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.273.1-273.1
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• 2014

Graphene, a two dimensional plane structure of $sp^2$ bonding, has been promised for a new material in many scientific fields such as physics, chemistry, and so on due to the unique properties. Chemical vapor deposition (CVD) method using transitional metals as a catalyst can synthesize large scale graphene with high quality and transfer on other substrates. However, it is difficult to control the number of graphene layers. Therefore, it is important to manipulate the number of graphene layers. In this work, homogeneous solid solution of Cu and Ni was used to control the number of graphene layers. Each films with different thickness ratio of Cu and Ni were deposited on $SiO_2/Si$ substrate. After annealing, it was confirmed that the thickness ratio accords with the composition ratio by X-ray diffraction (XRD). The synthesized graphene from CVD was analyzed via raman spectroscopy, UV-vis spectroscopy, and 4-point probe to evaluate the properties. Therefore, the number of graphene layers at the same growth condition was controlled, and the correlation between mole fraction of Ni and the number of graphene layers was investigated.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.210.1-210.1
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• 2014

The hexagonal boron nitride (h-BN) sheet, a 2D material like graphene sheet, is comprised of boron and nitrogen atoms. Similar to graphene, h-BN sheet has attractive mechanical properties while it has a wide band gap unlike graphene. Recently, many experimental groups studied the growth of single BN layer by chemical vapor deposition (CVD) method on the copper substrate. To study the initial stage of h-BN growth on the copper surface, we have performed density functional theory calculations. We investigate several adsorption sites of a boron or nitride atom on the Cu surfaces. Then, by increasing the number of adsorbed B and N atoms, we study formation behaviors of the BN flakes on the surface. Several types of BN flakes atoms such as triangular, linear, and hexagonal shapes are considered on the copper surface. We find that the formation of the BN flake in triangular shape is most favorable on the surface. On the basis of the theoretical results, we discuss the growth mechanism of h-BN layer on the copper surfaces in terms of its shapes in the initial stage of growth.

• Korean Journal of Materials Research
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• v.7 no.9
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• pp.811-823
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• 1997

차세대 반도체 배선분야에서, Cu박막은 현재의 AI을 대체할 물질로서 대두되고 있으며 CVD에 의한 선택적 증착은 Cu의 patterning과 관련하여 상당한 관심을 일으키고 있다. 본 연구에서는 (hfac)Cu(VTMS)의 유기원료를 사용하여, CVD공정변수, 운반기체, 표면 처리 공정에 따른 SiO$_{2}$, TiN, AI기판에 대한 선택성을조사하였다. 선택성은 저온(15$0^{\circ}C$), 저합(0.3Torr)에서 향상될 수 있었으며, 특히, HMDS in-situ-predosing공정에 의해 더욱 향상될 수 있었다. 모든 경우에 대해, H$_{2}$운반기체가 Ar 보다 짧은 incubation time과 높은 증착 속도가 얻어졌으며, Cu입자들의 크기가 작고 연결상태가 보다 양호하였다. 이는 H$_{2}$경우에 기판표면에 원료가 흡착되어 핵을 형성시키는 위치 (-OH)가 보다 많이 제공되기 때문으로 여겨진다. 이러한 미세구조의 차이는 H$_{2}$경우에 보다 낮은 비저항을 얻게 했다. HMDS in-situ predosing공정에 의한 Cu박막내 불순물 차이는 없었으며 뚜렷한 비저항의 차이도 나타나지 않았다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2017.05a
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• pp.116.1-116.1
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• 2017

본 연구는 PVD와 CVD를 동시에 사용한 하이브리드 공정시스템을 이용하여 Ti를 도핑한 Diamond-like carbon(DLC) 코팅 전극의 특성 분석에 대한 내용을 다루고 있다. DLC는 높은 경도, 낮은 마찰 계수, 화학적 안정성 등의 좋은 기계적 물성을 가지고 있어 주로 내마모성이 요구되는 분야에 주로 적용되어 왔다. 또한 DLC는 넓은 전위창 및 낮은 백그라운드 전류 등의 전기화학적 특성을 가지고 있어 최근 전극용으로 전도유망한 소재로 주목받고 있지만, 높은 비저항과 낮은 접착력은 여전히 극복해야할 문제로 남아있다. 본 연구에서는 Plasma enhanced chemical vapor deposition (PECVD) 법과 High power impulse magnetron sputtering (HiPIMS) 기법을 동시에 사용하여 Ti/TiC 하지층과 그 위에 Ti-DLC 막을 증착하였고, Ti 함량에 따른 DLC 박막의 특성변화를 살펴보았다. PVD/CVD 하이브리드 증착법에 의한 하지층은 DLC막과 기판사이의 밀착력을 향상시켰고, 기존 PECVD법과 비교하였을 때 하이브리드 증착법은 DLC 박막의 증착률을 크게 증가시켰다. DLC 박막에 소량의 Ti가 들어가면 C-C $sp^2$ 구조가 증가하여 전기적, 전기화학적 특성이 향상되었고, Ti의 함량이 일정 이상 증가하면 TiC의 영향을 받아 전기적, 전기화학적 특성이 나빠지는 것을 알 수 있었다. 본 연구에서는 DLC를 전극으로 활용하기 위해 전기적 및 전기화학적 특성을 향상시키는 연구에 집중하였지만, 산업에 활용하기 위해서 기계적 물성향상과 수명에 관한 추가적인 연구가 이루어 진다면 DLC 전극 분야 발전에 많은 기여를 할 수 있을 것이라 생각한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.579-579
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• 2012

Graphene has recently been a subject of much interest as a potential platform for future nanodevices such as flexible thin-film transistors, touch panels, and solar cells. And chemical vapor deposition (CVD) and related surface segregation techniques are a potentially scalable approach to synthesizing graphite films on a variety of metal substrates. The structural properties of such films have been studied by a number of methods, including Raman scattering, x-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM), and transmission electron microscopy (TEM). An understanding of the structural quality and thickness of the graphite films is of paramount importance both in improving growth procedures and understanding the resulting films' electronic properties. In this study, we synthesized the few-layered grapheneunder optimized condition to figure out the growth mechanism seen in CVD-grown graphenee by using various electron microscope. Especially, we observed directly film thickness, quality, nucleation site, and uniformity of grpahene by using AEM. The details will be discussed in my presentation.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.67.1-67.1
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• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.