• Title/Summary/Keyword: CPU Processing Time

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Parallel Processing of Pattern Recognition Algorithms for an Automatic Assembly System of Electronic Components (전자부품 조립공정의 자동화를 위한 형상인식 알고리즘의 병렬처리)

  • You, B.J.;Oh, Y.S.;Oh, S.R.;Bien, Z.
    • Proceedings of the KIEE Conference
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    • 1987.07a
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    • pp.260-264
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    • 1987
  • Algorithms to detect in real-time both position and orientation of rectangular type electronic components are developed for industrial vision. In order to conduct detection in real-time, parallel processing algorithm of image date which uses several control processor is proposed. Image processing area is divided into several regions which can be processed by each cpu. As a result, processing time is improved when two control processors are used and real-time pattern recognition of not-well-aligned components is accomplished.

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A study on the Circuit Designed for Bottle-neck Rejection and Effective PCI (병목 현상 제거 및 효율적인 PCI 회로 설계에 관한 연구)

  • 이인섭;강정용;김환용
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.4C
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    • pp.365-370
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    • 2002
  • In this paper external image multi-processing digital signal the transmit is the possibility of doing system with the PCI the design. The bottle-neck which it follows in transmission ratio limit of the CPU and the circumference machineries and tools against the image data which with the improve one thing becomes the processing with the real-time efficiently the transmit and the control is the possibility of doing structure the proposed. The also with the resource amount used 13% reduced which PCI fast data transfer and DMA function. The designed is operation verification against the function and the timing which use Max+plus II.

R Based Parallelization of a Climate Suitability Model to Predict Suitable Area of Maize in Korea (국내 옥수수 재배적지 예측을 위한 R 기반의 기후적합도 모델 병렬화)

  • Hyun, Shinwoo;Kim, Kwang Soo
    • Korean Journal of Agricultural and Forest Meteorology
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    • v.19 no.3
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    • pp.164-173
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    • 2017
  • Alternative cropping systems would be one of climate change adaptation options. Suitable areas for a crop could be identified using a climate suitability model. The EcoCrop model has been used to assess climate suitability of crops using monthly climate surfaces, e.g., the digital climate map at high spatial resolution. Still, a high-performance computing approach would be needed for assessment of climate suitability to take into account a complex terrain in Korea, which requires considerably large climate data sets. The objectives of this study were to implement a script for R, which is an open source statistics analysis platform, in order to use the EcoCrop model under a parallel computing environment and to assess climate suitability of maize using digital climate maps at high spatial resolution, e.g., 1 km. The total running time reduced as the number of CPU (Central Processing Unit) core increased although the speedup with increasing number of CPU cores was not linear. For example, the wall clock time for assessing climate suitability index at 1 km spatial resolution reduced by 90% with 16 CPU cores. However, it took about 1.5 time to compute climate suitability index compared with a theoretical time for the given number of CPU. Implementation of climate suitability assessment system based on the MPI (Message Passing Interface) would allow support for the digital climate map at ultra-high spatial resolution, e.g., 30m, which would help site-specific design of cropping system for climate change adaptation.

VDI deployment and performance analysys for multi-core-based applications (멀티코어 기반 어플리케이션 운용을 위한 데스크탑 가상화 구성 및 성능 분석)

  • Park, Junyong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.10
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    • pp.1432-1440
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    • 2022
  • Recently, as Virtual Desktop Infrastructure(VDI) is widely used not only in office work environments but also in workloads that use high-spec multi-core-based applications, the requirements for real-time and stability of VDI are increasing. Accordingly, the display protocol used for remote access in VDI and performance optimization of virtual machines have also become more important. In this paper, we propose two ways to configure desktop virtualization for multi-core-based application operation. First, we propose a codec configuration of a display protocol with optimal performance in a high load situation due to multi-processing. Second, we propose a virtual CPU scheduling optimization method to reduce scheduling delay in case of CPU contention between virtual machines. As a result of the test, it was confirmed that the H.264 codec of Blast Extreme showed the best and stable frame, and the scheduling performance of the virtual CPU was improved through scheduling optimization.

Fast Generation of Digital Hologram Based on Multi-GPU (Multi-GPU 기반의 고속 디지털 홀로그램 생성)

  • Song, Joong-Seok;Park, Jung-Sik;Seo, Young-Ho;Park, Jong-Il
    • Journal of Broadcast Engineering
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    • v.16 no.6
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    • pp.1009-1017
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    • 2011
  • Fast generation of digital hologram is of importance for real-time holography broadcasting. In this paper, we propose such a method that parallelizes the Computer-Generated Holography (CGH) algorithm for digital hologram generation and make it faster using Multi Graphic Processing Unit (Multi-GPU) with help of the Compute Unified Device Architecture (CUDA) and the Open Multi-Processing (OpenMP). In addition, we propose optimization methods such as fixation variable, vectorization, and loop unrolling for making the CGH algorithm much faster. Experimental results show that our method is about 9,700 times faster than a CPU-based one.

Design of Real-time Auto-Focusing System (실시간 자동 초점 조절 시스템의 설계)

  • Kim, Nam-Jin;Seo, Sam-Jun;Seo, Ho-Joon;Park, Gwi-Tae
    • Proceedings of the KIEE Conference
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    • 1997.11a
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    • pp.116-118
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    • 1997
  • The moving average filter in this paper, which has robust performance to the noise and can be easily implementable in hardware, is modified in view of real-time processing of the focus value. The simple hardware configurations are implemented to calculate the focus value in real-time. The stable controller of focus lens actuated by motors are designed. The hardware which are composed of EPLD, cheap vision chips, and CPU etc. are designed to perform the real-time calculation of focus value.

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Development of Real-time Blood Pressure Monitoring System using Radio Wave (전파를 이용한 실시간 혈압 모니터링 시스템 개발)

  • Jang, Dong-won;Eom, Sun-Yeong;Choe, Jae-Ik
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.05a
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    • pp.308-311
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    • 2015
  • Because worldwide interest in the health is increased, the real-time health monitoring system has been demanded to be more convenient non-contact and precise medical devices than conventional. Therefore we developed the blood pressure monitoring system using UWB(Ultra Wide Band) radio wave which contact to the human body through the radar and continuously collect a movement signal of the blood vessel. Then the collected data including pulse rate, systolic blood pressure, diastolic blood pressure is processed in real time. The system monitors and controls through a program-based embedded LCD(Liquid Crystal Display) using Qt GUI(Graphic User Interface) to be displayed in real time. We implement the system as a embedded system because of reducing the size of the limited resources. Existing PC GUI design mode is used relatively large memory, therefore it requires more CPU(Central Processing Unit) capacity and processing time.

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Implementation of ATPG for IdDQ testing in CMOS VLSI (CMOS VLSI의 IDDQ 테스팅을 위한 ATPG 구현)

  • 김강철;류진수;한석붕
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.3
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    • pp.176-186
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    • 1996
  • As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.

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Study of Dark Matter at e+e- Collider using KISTI-5 Supercomputer

  • Park, Kihong;Cho, Kihyeon
    • International Journal of Contents
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    • v.17 no.3
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    • pp.67-73
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    • 2021
  • Dark matter is barely known because it cannot be explained using the Standard Model. In addition, dark matter has not been detected yet. It is currently being explored through various ways. In this paper, we studied dark matter in an electron-positron collider using MadGraph5. The signal channel is e+e- → 𝜇+𝜇-A' where A' decays to dimuon. We studied the cross-section by increasing the center-of-mass energy. Central processing unit (CPU) time of simulation was compared with that using a local Linux machine and a KISTI-5 supercomputer (Knight Landing and Skylake). Furthermore, one or more cores were used for comparing CPU time among machines. Results of this study will enable the exploration of dark matter in electron-positron experiments. This study also serves as a reference for optimizing high-energy physics simulation toolkits.

IoT Malware Detection and Family Classification Using Entropy Time Series Data Extraction and Recurrent Neural Networks (엔트로피 시계열 데이터 추출과 순환 신경망을 이용한 IoT 악성코드 탐지와 패밀리 분류)

  • Kim, Youngho;Lee, Hyunjong;Hwang, Doosung
    • KIPS Transactions on Software and Data Engineering
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    • v.11 no.5
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    • pp.197-202
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    • 2022
  • IoT (Internet of Things) devices are being attacked by malware due to many security vulnerabilities, such as the use of weak IDs/passwords and unauthenticated firmware updates. However, due to the diversity of CPU architectures, it is difficult to set up a malware analysis environment and design features. In this paper, we design time series features using the byte sequence of executable files to represent independent features of CPU architectures, and analyze them using recurrent neural networks. The proposed feature is a fixed-length time series pattern extracted from the byte sequence by calculating partial entropy and applying linear interpolation. Temporary changes in the extracted feature are analyzed by RNN and LSTM. In the experiment, the IoT malware detection showed high performance, while low performance was analyzed in the malware family classification. When the entropy patterns for each malware family were compared visually, the Tsunami and Gafgyt families showed similar patterns, resulting in low performance. LSTM is more suitable than RNN for learning temporal changes in the proposed malware features.