• Proceedings of the KSR Conference
• /
• 2008.06a
• /
• pp.1809-1815
• /
• 2008

This experiment simulated the fire driven flow of an underground station through parallel processing method. Fire analysis program FDS(Fire Dynamics Simulation), using LES(Large Eddy Simulation), has been used and a 6-node parallel cluster, each node with 3.0Ghz_2set installed, has been used for parallel computation. Simulation model was based on the Kwangju-geumnan subway station. Underground station, and the total time for simulation was set at 600s. First, the whole underground passage was divided to 1-Mesh and 8-Mesh in order to compare the parallel computation of a single CPU and Multi-CPU. With matrix numbers($15{\times}10^6$) more than what a single CPU can handle, fire driven flow from the center of the platform and the subway itself was analyzed. As a result, there seemed to be almost no difference between the single CPU's result and the Multi-CPU's ones. $3{\times}10^6$ grid point one employed to test the computing time with 2CPU and 7CPU computation were computable two times and fire times faster than 1CPU respectively. In this study it was confirmed that CPU could be overcome by using parallel computation.

• Journal of the Korea Society of Computer and Information
• /
• v.14 no.12
• /
• pp.17-24
• /
• 2009

More recently, the Green Computing have become a important issue in all fields of industry. The energy efficiency cannot be over-emphasized. Microprocessor companies such as Intel Corporation design processors with taking both energy efficiency and performance into account. Nevertheless, general computer users typically utilize the CPU overclocking to enhance the application performance. The overclocking is traditionally considered as an evil in terms of the power consumption. In this paper, we present effective CPU overclocking schemes, which raise CPU frequency while keeping current CPU supply voltage for energy reduction and performance improvement. The proposed scheme gain both energy reduction and performance improvement. Evaluation results show that our proposed schemes reduce the processor execution time as much as 17% and total computer system energy as much as 5%, respectively. In addition, our effective CPU overclocking schemes reduce the Energy Delay Product (EDP) as much as 22%, on average.

• The Journal of the Acoustical Society of Korea
• /
• v.4 no.2
• /
• pp.36-47
• /
• 1985

본 논문에서는 기존의 ICE 기능을 갖춘 사용이 간편하고, 쉽게 이동이 가능한 저가격 범용 8비 트 마이크로프로세서의 실시간 에뮬레이터를 설계, 제작하고자 한다. ICE의 기능을 구현하기 위해서2개 의 보드 즉 에뮬레이션 보드와 콘트롤 보드를 사용하는 구조로 고안하였다. 에뮬레이션 보드에는 CPU 8085를 사용하고, 콘트롤 보드에는 표적시스템의 CPU와 같은 CPU를 사용하였다. 이러한 구조는 표적 CPU가 바뀔 때 콘트롤 보드만 교환하면 된다는 점에서 실용적이다. 에뮬레이션 보드는 범용 8비트 마 이크로프로세서에 대해서, 콘트롤 보드는 표적 CPU가 Z-80인 시스템에 대해서 제작하였다. 또한, 에뮬 레이터의 기능에 의해, 표적 CPU 자체의 기능이 상실됨을 회복시켰다.

• The Journal of Society for e-Business Studies
• /
• v.7 no.3
• /
• pp.203-218
• /
• 2002

According as development of networks and increasing on Internet service, For the performance increase of K4 Firewall require that hardware be installed of 2 CPU or 4 CPU instead of 1 CPU. Output of performance test among 1CPU, 2CPU, and 4CPU of K4 Firewall system has not any efficient about increasing multiple CPUs. K4 Firewall put performance on setting on demon of packet filtering rules and Network Address Translate and Authentication and Proxy services. Performance results that setting after security rules are less 2％ Packet Filtering, 8％-11％ NAT, 18％-20％ Proxy and Authentication services than setting before security rules on K4 Firewall System. NAT and Proxy service have decrease of performance. This performance result comes in useful for research and development on K4 Firewall System.

• Aerospace Engineering and Technology
• /
• v.12 no.2
• /
• pp.131-139
• /
• 2013

This paper describes the design and implementation of a small avionics unit based on soft CPU. A small avionics unit is developed with the soft CPU which can be wholly implemented in FPGA using logic synthesis. Design and integration of a modular architecture for versatile, reconfigurable and re-adaptable is presented with the Nios-II processor. To gain modular architecture, both at main board and sub-board level, attention has been paid to the selection of interfaces and an adequate data and power bus.

• Proceedings of the Korean Information Science Society Conference
• /
• 1999.10c
• /
• pp.21-23
• /
• 1999

CPU에게 최상위 우선순위가 할당된 고정 우선순위 버스 프로토콜에서는 CPU와 DMA 컨트롤러의 버스 요구가 충돌할 경우 DMA 전송이 지연된다. 본 논문에서는 CPU와 다수의 DMA 컨트롤러가 시스템 버스를 공유하는 환경에서 DAM I/O 요구의 최악 응답시간을 분석하는 기법을 제안한다. 제안하는 최악 응답시간 분석 기법은 다음의 세단계로 구성되어 있다. 첫 번째 단계에서는 CPU 상에서 수행중인 각 CPU 태스크별로 최악 버스 요구 패턴을 구한다. 두 번째 단계에서는 이들 CPU 태스크의 최악 버스 요구 패턴을 모두 통합해 CPU 전체의 최악 버스 요구 패턴을 구한다. 최종 세 번째 단계에서는 CPU의 최악 버스 요구 패턴으로부터 DMA 컨트롤러의 버스 가용량을 구하고 DMA I/O 요구의 최악 응답시간을 산출한다. 모의 실험을 통해 제안하는 분석 기법일 일반적인 DMA전송량에 대해 20% 오차 범위 이내에서 안전한 응답시간을 산출함을 보였다.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.32 no.4
• /
• pp.255-265
• /
• 2008

This paper presents the optimization process of evaporator for a vapor compression cooling system for high heat flux CPU. The CPU thermal capacity was given by 300W. Evaporating temperature and mass flow rate were $18^{\circ}C$ and 0.00182kg/s respectively. R134a was used as a working fluid. Channel width(CW) and height(CH) were selected as design factors. And thermal resistance, surface temperature of CPU, degree of superheat, and pressure drop were taken as objective responses. Fractional factorial DOE was used in screening phase and RSM(Response Surface Method) was used in optimization phase. As a result, CW of 2.5mm, CH of 2.5mm, and CL of 484mm were taken as an optimum geometry. Surface temperature of CPU and thermal resistance were $33^{\circ}C\;and\;0.0502^{\circ}C/W$ respectively. Thermal resistance of evaporator designed in this study was significantly lower than that of other cooling systems such as water cooling system and thermosyphon system. It was found that the evaporator considered in this work can be a excellent candidate for a high heat flux CPU cooling system.

• Journal of IKEEE
• /
• v.21 no.3
• /
• pp.211-218
• /
• 2017

This paper proposes the self-powered solar tracker system without CPU. Conventional solar tracker system occurs the problem of cost and durability because of using CPU. In addition, this system has effects from installation site and environment. The proposed solar tracker system without CPU is possible to achieve the high efficiency because it tracks the maximum of the light source. The validity of proposed solar tracking system is verified with experiment results.

• International Journal of Computer Science & Network Security
• /
• v.21 no.1
• /
• pp.19-26
• /
• 2021

CPU is considered the main and most important resource in the computer system. The CPU scheduling is defined as a procedure that determines which process will enter the CPU to be executed, and another process will be waiting for its turn to be performed. CPU management scheduling algorithms are the major service in the operating systems that fulfill the maximum utilization of the CPU. This article aims to review the studies on the CPU scheduling algorithms towards comparing which is the best algorithm. After we conducted a review of the Round Robin, Shortest Job First, First Come First Served, and Priority algorithms, we found that several researchers have suggested various ways to improve CPU optimization criteria through different algorithms to improve the waiting time, response time, and turnaround time but there is no algorithm is better in all criteria.

• The KIPS Transactions:PartA
• /
• v.19A no.3
• /
• pp.139-146
• /
• 2012

In the server cluster environment, one of the ways saving energy is to control server's power according to traffic conditions. This is to determine the ON/OFF state of servers according to energy usage of data center and each server. To do this, we need a way to estimate each server's energy. In this paper, we use a software-based power consumption estimation model because it is more efficient than the hardware model using power meter in terms of energy and cost. The traditional software-based power consumption estimation model has a drawback in that it doesn't know well the computing status of servers because it uses only the idle status field of CPU. Therefore it doesn't estimate consumption power effectively. In this paper, we present a CPU field based power consumption estimation model to estimate more accurate than the two traditional models (CPU/Disk/Memory utilization based power consumption estimation model and CPU idle utilization based power consumption estimation model) by using the various status fields of CPU to get the CPU status of servers and the overall status of system. We performed experiments using 2 PCs and compared the power consumption estimated by the power consumption model (software) with that measured by the power meter (hardware). The experimental results show that the traditional model has about 8-15% average error rate but our proposed model has about 2% average error rate.