• ETRI Journal
• /
• v.33 no.3
• /
• pp.366-373
• /
• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

• Transactions on Electrical and Electronic Materials
• /
• v.17 no.5
• /
• pp.261-269
• /
• 2016

A high-performance transmit/receive (T/R) switch is essential for every radio-frequency (RF) device. This paper proposes a T/R switch that is designed in the CEDEC 0.13 μm complementary metal-oxide-semiconductor (CMOS) technology for 2.4 GHz ISM-band RF applications. The switch exhibits a 1 dB insertion loss, a 28.6 dB isolation, and a 35.8 dBm power-handling capacity in the transmit mode; meanwhile, for the 1.8 V/0 V control voltages, a 1.1 dB insertion loss and a 19.4 dB isolation were exhibited with an extremely-low power dissipation of 377.14 μW in the receive mode. Besides, the variations of the insertion loss and the isolation of the switch for a temperature change from - 25℃ to 125℃ are 0.019 dB and 0.095 dB, respectively. To obtain a lucrative performance, an active inductor-based resonant circuit, body floating, a transistor W/L optimization, and an isolated CMOS structure were adopted for the switch design. Further, due to the avoidance of bulky inductors and capacitors, a very small chip size of 0.0207 mm² that is the lowest-ever reported chip area for this frequency band was achieved.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
• /
• 2003.11a
• /
• pp.234-238
• /
• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a $0.25-{\mu}m$ standard CMOS Process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier, Total power dissipation is 7.5 mW.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.1
• /
• pp.33-38
• /
• 2017

In this paper, a 4-channel common-cathode VCSEL diode driver array with 3.125 Gb/s per channel operation speed is realized. In order to achieve faster speed of the switching main driver with relatively large transistors, the transmitter array chip consists of a pre-amplifier with active inductor stage and also an input buffer with modified equalizer, which leads to bandwidth extension and reduced current consumption. The utilized VCSEL diode provides inherently 2.2 V forward bias voltage, $50{\Omega}$ resistance, and 850 fF capacitance. In addition, the main driver based upon current steering technique is designed, so that two individual current sources can provide bias currents of 3.0 mA and modulation currents of 3.3 mA to VCSEL diodes. The proposed 4-channel VCSEL driver array has been implemented by using a $0.11-{\mu}m$ CMOS technology, and the chip core occupies the area of $0.15{\times}0.18{\mu}m^2$ and dissipates 22.3 mW per channel.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.3
• /
• pp.34-41
• /
• 2011

This paper presents a wide tuning range, fine-resolution DCO (Digitally Controlled Oscillator) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. To cover the wide tuning range, an automatic three-step coarse tuning scheme is proposed. The DCO total frequency tuning range is 1.4 GHz (2.1 GHz to 3.5 GHz), it is 58 % at 2.4 GHz. An effective frequency resolution is 0.14 kHz/LSB. The proposed DCO is implemented in 0.13 ${\mu}m$ CMOS process. The total power consumption is 6.6 mW from a 1.2 V supply voltage. The phase noise of the DCO output at 2.4 GHz is -120.67 dBc/Hz at 1 MHz offset.

• 한국정보통신설비학회:학술대회논문집
• /
• 2007.08a
• /
• pp.11-14
• /
• 2007

CMOS technology 기반의 고주파 직접회로에서는 충분한 이득과 안정성을 얻기 위하여 inductor, capacitor와 같은 수동 소자를 적절히 사용하여 설계하여야 한다. 이와 같은 수동 소자는 CMOS 집적회로에서 넓은 면적을 차지하는 단점이 있다. 고주파 증폭기의 부하를 능동 소자로 대체하게 되면 작은 크기로 회로의 제작이 가능하게 되나, 능동 소자는 수동 소자에 비하여 선형 특성이 좋지 않기 때문에 실제로 고주파 증폭기 설계에 사용하지 않는다. 본 논문에서는 이와 같은 능동 소자의 비선형성을 억제하면서, 동시에 회로의 크기를 줄일 수 있는 기능성 능동 부하를 적용한 고주파 증폭기를 설계하였다. 기능성 능동 부하는 2개의 MOSFET은 대칭으로 연결된 구조를 가지며, 하나의 MOSFET은 일반적인 load로 동작하며, 다른 MOSFET은 gate에 가변 전압을 인가함으로써, 증폭기의 전달함수를 변화시킬 수 있다. 이와 같은 특성을 이용하여 고주파 증폭기의 선형성을 보상할 수가 있다.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.873-876
• /
• 2005

A low noise amplifier(LNA) using electro-magnetic field simulator is designed in standard 0.25um CMOS process. Integrated spiral inductor is simulated using EM field solver. Then LNA is simulated with active device, capacitor and simulated inductor by EM field solver. A S11 and S21 of -15.45dB and 17.8dB at 2.3GHz as simulation results was achieved. A Noise Figure is 2.92dB. And Measurements show a S11 and S21 of -12.4dB and 17.8dB at 2.3GHz. A Noise Figure of 3.3dB was achieved.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.1
• /
• pp.28-35
• /
• 2007

This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistor size for the cascaded stages is inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for the sake of measurements. This chip has been fabricated in $0.13{\mu}m$ 1P8M CMOS process and the total power consumption is 113mW with 1V supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200MHz at 5-GSample/sec.

• Proceedings of the IEEK Conference
• /
• 2003.11c
• /
• pp.32-36
• /
• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a 0.25-$\mu\textrm{m}$ standard CMOS process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier. Total power dissipation is 7.5 mW.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.909-912
• /
• 2005

According to miniaturization trend of rehabilitation medical equipment such as hearing aid, study to replace previous complex system with semiconductor SOC (System-on-Chip) chip becomes lively. In this study, after investigating of existent hearing aid performance in circuit design approach, low electric power consuming, single power supply (1.4V battery) CMOSS OP AMP was designed. Analog circuit design tools such as Hspice and Cadence were used for circuit simulation and implementing layout design. This study shows technical methods particularly for layout design. The work is done in pmos and nmos active element layout design in addition to passive element design such as resister, capacitor and inductor.