• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.1-8
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• 2004

This paper describes the design of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been designed in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3 metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$ and the estimated power dissipation is less than 900 ㎽ with a single 5 V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.11-17
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• 2004

This paper describes the implementation of monolithic optical transceiver circuitry being used as a part of the fiber optic modules. It has been fabricated in 0.6 ${\mu}{\textrm}{m}$ 2-poly 3-metal silicon CMOS analog technology and operates at 155.52 Mbps(STM-1) data rates. It drives laser diode to transmit intensity modulated optical signal according to 155.52 Mbps electrical data from system. Also, it receives 155.52 Mbps optical data that transmitted from other systems and converts it to electrical data using photo diode and amplifier. To avoid noise and interference between transmitter and receiver on one chip, layout techniques such as special placement, power supply separation, guard ring, and protection wall were used in the design. The die area is 4 ${\times}$ 4 $\textrm{mm}^2$, and it has 32.3 ps rms and 335.9 ps peak to peak jitter on loopback testing. the measured power dissipation of whole chip is 1.15 W(230 mW) with a single 5 V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.68-75
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• 2007

A single chip NFC transceiver supporting not only NFC active and passive mode but also 13.56MHz RFID reader and tag mode was designed and fabricated. The proposed NFC transceiver can operate as a RFID tag even without external power supply which has dual antenna structure for initiator and target. The area increment due to additional target antenna is negligible because the target antenna is constructed by using a shielding layer of initiator antenna. The analog front end circuit of the proposed NFC transceiver consists of a transmitter and receiver of reader/writer block supporting NFC initiator or RFID reader mode, and a tag circuit for target of passive NFC mode or RFID tag mode. The maximum baud rate of the proposed NFC device is 212kbps by using UART serial interface. The chip has been designed and fabricated using a Magnachip's $0.35{\mu}m$ double poly 4-metal CMOS process, and the effective area of the chip is 2200um by 3600um.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.4
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• pp.49-58
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• 2014

A low-swing differential near-ground signaling (NGS) transceiver for low-power high-speed mobile I/O interface is presented. The proposed transmitter adopts an on-chip regulated programmable-swing voltage-mode driver and a pre-driver with asymmetric rising/falling time. The proposed receiver utilizes a new multiple gain-path differential amplifier with feed-forward capacitors that boost high-frequency gain. Also, the receiver incorporates a new adaptive bias generator to compensate the input common-mode variation due to the variable output swing of the transmitter and to minimize the current mismatch of the receiver's input stage amplifier. The use of the new simple and effective impedance matching techniques applied in the transmitter and receiver results in good signal integrity and high power efficiency. The proposed transceiver designed in a 65-nm CMOS technology achieves a data rate of 13 Gbps/channel and 0.3 pJ/bit (= 0.3 mW/Gbps) high power efficiency over a 10 cm FR4 printed circuit board.

• Information and Communications Magazine
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• v.29 no.11
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• pp.81-93
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• 2012

60GHz 주파수는 최대 9GHz 까지 엄청난 대역폭을 활용하여 Gbps급의 무선전송이 가능한 대역으로서, 최근 이 대역을 댁내 무선전송장치 및 초고속 무선랜에 활용하기 위한 연구가 활발히 진행되고 있다. 이와 같이 60GHz에 대한 관심도가 높아진 이유는, 밀리미터파 통신이 기존에는 무선 백홀용으로 주로 사용되었던것에 비해 지금은 가정 및 사무실내에서의 초고속 네트워크 또는 영상가전에서의 무선 전송장치 등 응용분야의 다변화가 예상됨에 따라, ISM 대역이면서 광대역을 활용할 수 있는 60GHz가 급부상하게 된 것으로 본다. 이와 함께 CMOS 칩기술의 꾸준한 발전으로 현재는 수 십 나노공정을 이용하여 테라헤르쯔 대역에서도 동작하는 칩이 발표되고 있는 바 그동안 60GHz 시장 확산의 가장 큰 걸림돌이 었던 무선 전송장치의 높은 가격, 사이즈, 소모전력의 문제를 한꺼번에 해결할 수 있게 된 점도 이유중 하나이다. 따라서 이와 관련하여 본고에서는 ETRI와 KETI를 중심으로 진행되어 온 "60GHz 무선 전송장치에 탑재 가능한 범용 CMOS 송수신 칩 및 이를 활용한 빔포밍 트랜시버 기술에 관한 연구"를 소개하고자 한다.

• 한국정보통신설비학회:학술대회논문집
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• 2003.08a
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• pp.177-179
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• 2003

본 논문에서는 $0.35{\mu}m$ CMOS 공정을 이용하여 2.5 Gbps로 동작하는 광 송수신기를 설계하였다. 광 송수신기의 구성을 보자면, 전기 신호를 빛 신호로 전환하여 주는 레이저 다이오드(LD) 구동부와 레이저 다이오드에서 나오는 빛 신호를 수신하여 이를 다시 전기 신호로 바꿔주는 포토 다이오드(PD) 구동 부분으로 구성된다. LD 구동부는 LD의 문턱전류 이상을 공급하는 바이어스 부분과 신호레벨의 모듈레이션 전류를 공급하는 부분으로 구성된다. 디자인된 송신기는 바이어스 전류를 10 mA 정도 공급하여주며, 모듈레이션 전류를 15 mA 정도 공급한다. 수신기는 current decision 부분과 output buffer 부분으로 구성되어 PD로부터 나오는 전류를 다시 디지털 레벨의 전압신호로 바꾸어 주며 디자인된 수신기는 넓은 동작 영역을 가진다.

• Journal of Advanced Marine Engineering and Technology
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• v.37 no.4
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• pp.425-430
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• 2013

Robust and high speed underwater communication is severely limited when compared to communications in terrestial. In free space, RF communication operates over long distances at high data rates. However, the obstacle in seawater is the severe attenuation due to the conducting nature. Acoustic modems are capable of long range communication up to several tens of kilometers, but it has low data-rate, high power consumption and low propagation speed. An alternative means of underwater communication is based on optics, wherein high data rates are possible. In this paper, the characteristics of underwater channel in the range of visible wavelength is investigated. And the possibility of optical wireless communication in underwater is also described. The LED-based transceiver and CMOS sensor module are integrated in the system, and the performance of image transmission was demonstrated.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.38-44
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• 2008

In this paper, we introduce an low complexity and low power IR-UWB (impulse radio ultra wideband) baseband transceiver for wireless sensor network. The proposed baseband, implemented by TSMC 0.18um CMOS technology, has a simple structure in which a simplified packet structure and a digital synchronizer with 1-bit sampler to detect incoming pulses are used. Besides, clock gating method using gated clock cell as well as customized clock domain division can reduce the total power consumption drastically. As a result, the proposed baseband has about 23K digital gates with an internal memory of 2Kbytes and achieves about 1.8mW@1Mbps power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.93-100
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• 2009

This paper presents a step up four channel DC-DC converter using charge pump voltage doubler structure. Our goal is to design and implement DC-DC converter for capacitive SP4T RF MEMS switch in front end module in wireless transceiver system. Charge pump structure is small and consume low power 3.3V input voltage is boosted by DC-DC Converter to $11.3{\pm}0.1V$, $12.4{\pm}0.1V$, $14.1{\pm}0.2V$ output voltage With 10MHz switching frequency. By using voltage level shifter structure, output of DC-DC converter is selected by 3.3V four channel selection signals and transferred to capacitive MEMS devices. External passive devices are not used for driving DC-DC converter. The total chip area is $2.8{\times}2.1mm^2$ including pads and the power consumption is 7.52mW, 7.82mW, 8.61mW.