• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.309-312
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• 2002

In this paper, we discuss the design of high gain low noise amplifier by using the 0.2sum CMOS technology. A cascode inverter is adopted to implement the low noise amplifier. The proposed cascode inverter LNA is one stage amplifier with a voltage reference and without choke inductors. The designed 2.4GHz LNA achieves a power gain of 25dB, a noise figure of 2.2dB, and power consumption of 255㎽ at 2.5V power supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.358-365
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• 2008

A differential-gain-controlled LNA is designed and implemented in 0.18 um CMOS technology for $3.1{\sim}4.8GHz$ UWB system. In high gain mode, measurements show a differential power gain of $14.1{\sim}15.8dB,\;13.3{\sim}15dB$, respectably, an input return loss higher then 10dB, an input IP3 of -19.3 dBm, a noise figure of $4.85{\sim}5.09dB$, while consuming only 19.8 mW of power from a 1.8V DC supply. In low gain mode, measurements show a differential power gain of $-6.1{\sim}-4.2dB,\;-7.6{\sim}-5.6dB$, respectably, an input return loss higher then 10dB, an input IP3 of -1.45 dBm, a noise figure of $8.8{\sim}10.3dB$, while consuming only 5.4mW of power from a 1.8V DC supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.191-194
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• 2000

A 2.4 GHz single ended two stage low noise amplifier(LNA) is designed for Bluetooth application. The circuit was implemented in a standard digital 0.25 $\mu\textrm{m}$ CMOS process with one poly and five metal layers. At 2.4 GHz, the LNA dissipates 34.5 mW from a 2.5V power supply voltage and provides 24.6 dB power gain, 2.85 dB minimum noise figure, -66.3 dB reverse isolation, and an output 1-dB compression level of 8.5 dBm.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.242-246
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• 2012

This paper presents an integrated low noise and highly linear wideband RF front-end for a digital terrestrial and cable TV tuner, which are used as a part of double-conversion TV tuner. The low noise amplifier (LNA) has a low noise figure and high linearity by adopting a noise canceling technique based on current amplification. The up-conversion mixer and SAW buffer have high linearity by employing a third order intermodulation cancellation technique. The proposed RF front-end is designed in a $0.18{\mu}m$ CMOS and draws 60 mA from a 1.8 V supply voltage. The RF front-end shows a voltage gain of 30 dB, an average single side-band noise figure of 4.2 dB, an IIP2 of 40 dBm, and an IIP3 of -4.5 dBm for the entire band from 48 MHz to 862Hz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.40-48
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• 2013

This paper presents multi-channel transimpedance amplifier(TIA) arrays in short-range LADAR systems for unmanned vehicles, by using a 0.18um CMOS technology. Two $4{\times}4$ channel TIA arrays including a voltage-mode INV-TIA and a current-mode CG-TIA are introduced. First, the INV-TIA consists of a inverter stage with a feedback resistor and a CML output buffer with virtual ground so as to achieve low noise, low power, easy current control for gain and impedance. Second, the CG-TIA utilizes a bias from on-chip bandgap reference and exploits a source-follower for high-frequency peaking, yielding 1.26 times smaller chip area per channel than INV-TIA. Post-layout simulations demonstrate that the INV-TIA achieves 57.5-dB${\Omega}$ transimpedance gain, 340-MHz bandwidth, 3.7-pA/sqrt(Hz) average noise current spectral density, and 2.84mW power dissipation, whereas the CG-TIA obtains 54.5-dB${\Omega}$ transimpedance gain, 360-MHz bandwidth, 9.17-pA/sqrt(Hz) average noise current spectral density, and 4.24mW power dissipation. Yet, the pulse simulations reveal that the CG-TIA array shows better output pulses in the range of 200-500-Mb/s operations.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.27-37
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• 1999

A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.51-57
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• 2010

A dual-mode direct conversion receiver is developed in $0.13\;{\mu}m$ RF CMOS process for IEEE 802.11n based wireless LAN and IEEE 802.16e based mobile WiMAX application. The RF receiver covers the frequency band between 2.3 and 2.7 GHz. Three-step gain control is realized in LNA by using current steering technique. Current bleeding technique is applied to the down-conversion mixer in order to lower the flicker noise. A frequency divide-by-2 circuit is included in the receiver for LO I/Q differential signal generation. The receiver consumes 56 mA at 1.4 V supply voltage including all LO buffers. Measured results show a power gain of 32 dB, a noise figure of 4.8 dB, a output $P_{1dB}$ of +6 dBm over the entire band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1055-1063
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• 2013

Low noise amplifiers(LNAs) are an integral component of RF receivers and are frequently required to operate at wide frequency bands for various wireless systems. For wideband operation, important performance metrics such as voltage gain, return loss, noise figures and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high input matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor between gate and drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this LNA is $0.202mm^2$, including pads. Measurement results illustrate that input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 7~8 dB over 1.5~13 GHz. In addition, good linearity(IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.758-765
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• 2018

This paper presents a 24-GHz frequency-modulated continuous wave(FMCW) radar transceiver with two Rx and one Tx channels in 65-nm complementary metal-oxide-semiconductor(CMOS) process and implemented it on a radar system using the developed transceiver chip. The transceiver chip includes a $14{\times}$ frequency multiplier, low-noise amplifier, down-conversion mixer, and power amplifier(PA). The transmitter achieves >10 dBm output power from 23.8 to 24.36 GHz and the phase noise is -97.3 GHz/Hz at a 1-MHz offset. The receiver achieves 25.2 dB conversion gain and output $P_{1dB}$ of -31.7 dBm. The transceiver consumes 295 mW of power and occupies an area of $1.63{\times}1.6mm^2$. The radar system is fabricated on a low-loss Duroid printed circuit board(PCB) stacked on the low-cost FR4 PCBs. The chip and antenna are placed on the Duroid PCB with interconnects and bias, gain blocks and FMCW signal-generating circuitry are mounted on the FR4 PCB. The transmit antenna is a $4{\times}4$ patch array with 14.76 dBi gain and receiving antennas are two $4{\times}2$ patch antennas with a gain of 11.77 dBi. The operation of the radar is evaluated and confirmed by detecting the range and azimuthal angle of the corner reflectors.