• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.897-904
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• 2011

In this paper, a novel circuit topology of a low-noise amplifier tunable at 1.8GHz band for PCS and 2.4GHz band for WLAN using a CMOS active inductor is proposed. This circuit topology to reduce higher noise figure of the low noise amplifier with the CMOS active load is analyzed. Furthermore, the noise canceling technique is adopted to reduce more the noise figure. The noise figure of the proposed circuit topology is analyzed and simulated in $0.18{\mu}m$ CMOS process technology. Thus, the simulation results exhibit that the noise performance enhancement of the tunable low noise amplifier is about 3.4dB, which is mainly due to the proposed new circuit topology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.647-648
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• 2016

본 논문에서는 차량용 레이더를 위한 저 전력 24GHz CMOS 저 잡음 증폭기를 제안한다. 이러한 회로는 1.8볼트 전원에서 동작하며, 저 전력에서도 높은 전압 이득과 낮은 잡음지수를 가지도록 설계되어 있다. 제안한 회로는 TSMC $0.13{\mu}m$ 고주파 CMOS 공정으로 구현되어 있다. 제안한 회로는 최근 발표된 연구결과에 비해 저 전력동작에서 높은 전압이득 및 낮은 잡음지수 특성을 보였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.753-754
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• 2014

본 논문에서는 차량 충돌 예방 장거리 레이더용 고 이득 및 저 잡음 77GHz CMOS 저 잡음 증폭기를 제안한다. 이러한 회로는 2볼트 전원전압 및 77GHz의 주파수에서 동작한다. 이러한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정($f_T/f_{MAX}=120/140GHz$)으로 설계되어 있다. 전체 칩 면적을 줄이기 위해 실제 수동형 인덕터 대신 전송선을 이용하였다. 제안한 회로는 최근 발표된 연구결과에 비해 34.33dB의 가장 높은 전압이득과 5.6dB의 가장 낮은 잡음지수 특성을 보였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.158-165
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• 2013

In this paper, a new circuit topology of an ultra-wideband (UWB) 3.1-10.6GHz CMOS low noise amplifier is presented. The proposed UWB low noise amplifier is designed utilizing RC feedback and LC filter networks which can provide good input impedance matching. In this design, the current-reused topology is adopted to reduce the power consumption and the inductor-peaking technique is applied for the purpose of bandwidth extension. The performance results of this UWB low noise amplifier simulated in $0.18-{\mu}m$ CMOS process technology exhibit a power gain of 14-14.9dB, an input matching of better than -10.8dB, gain flatness of 0.9dB, and a noise figure of 2.7-3.3dB in the frequency range of 3.1-10.6GHz. In addition, the input IP3 is -5dBm and the power consumption is 12.5mW.

• Journal of Korea Multimedia Society
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• v.6 no.1
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• pp.161-166
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• 2003

This paper presents a high gain LNA for a bluetooth application using 0.25$\mu\textrm{m}$ CMOS technology. The conventional one stage LNA has a low power gain. The presented one stage LNA using a cascode inverter LNA with a voltage reference and without a choke inductor has an improved Power gain. Simulation results of the 2.4GHz designed LNA shows a high power gain of 21dB, a noise figure of 2.2dB, and the power consumption of 255mW at 2.5V power supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.199-207
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• 2011

A Ku-band low noise amplifier has been designed and fabricated by using 0.25 um SiGe BiCMOS process. The developed Ku-band LNA RFIC which has been designed with hetero-junction bipolar transistor(HBT) in the BiCMOS process have noise figure about 2.0 dB and linear gain over 19 dB in the frequency range from 9 GHz to 14 GHz. Optimization technique for p-tap value and electro-magnetic(EM) simulation technique had been used to overcome the inaccuracy in the PDK provided from the foundry service company and to supply the insufficient inductor library. The finally fabricated low noise amplifier of two fabrication runs has been implemented with the size of $0.65\;mm{\times}0.55\;mm$. The pure amplifier circuit layout with the reduced size of $0.4\;mm{\times}0.4\;mm$ without the input and output RF pads and DC bais pads has been incorporated as low noise amplication stages in the multi-function RFIC for the active phased array antenna of Ku-band satellite VSAT.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.393-396
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• 2018

Herein, a 94-GHz low-noise amplifier (LNA) using the 65-nm CMOS process is presented. The LNA is composed of a four-stage differential common-source amplifier and impedance matching is accomplished with transformers. The fabricated LNA chip shows a peak gain of 25 dB at 94 GHz and has a 3-dB bandwidth at 5.5 GHz. The chip consumes 46 mW of DC power from a 1.2-V supply, and the total chip area, including the pads, is $0.3mm^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.696-697
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• 2016

본 논문은 5.25-GHz BiCMOS 저 잡음 증폭기를 위한 바이어스 회로를 제안한다. 이러한 회로는 1볼트 전원에서 동작하며, 저전압 및 저전력으로 동작하도록 설계되어 있다. 제안한 회로는 $0.18{\mu}m$ SiGe HBT BiCMOS로 설계하였다. 이러한 회로는 밴드 갭 참조회로 (band-gap reference circuit)를 사용하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.10
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• pp.832-835
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• 2017

In this paper, V-band differential low noise amplifier(LNA) using 65-nm CMOS process for high speed wireless data communication is presented. The LNA is composed of 3-stage common-source differential amplifiers with neutralization of feedback capacitances using MOS capacitors and impedance matching utilizing transformers. The fabricated LNA has a peak gain of 23 dB at 63 GHz and 3 dB bandwidth of 6 GHz. The chip area of LNA is $0.3mm^2$ and the LNA consumes 32 mW DC power from 1.2 V supply voltage.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.671-674
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• 1998

본 논문에서는 최근 급격히 수요가 증대하고 있는 휴대용 단말기의 수신기 선단에 사용되는 저잡음 증폭기(LNA)를 0.6㎛ CMOS공정 파라미터를 사용하여 설계하였다. 설계된 LNA는 전원 전압 ±1.2v, 900㎒대에서 동작하는 전류 재사용방식의 적층 CMOS구조로서 시뮬레이션 결과 전력소모가 9.45㎽, 전력이득은 23.7dB, 선형지수 OIP3는 7.6dBm을 나타내어 저전력 저잡음 특성을 얻었다. 사용된 인덕터의 Q는 3.5이다.