• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.11
• /
• pp.1055-1063
• /
• 2013

Low noise amplifiers(LNAs) are an integral component of RF receivers and are frequently required to operate at wide frequency bands for various wireless systems. For wideband operation, important performance metrics such as voltage gain, return loss, noise figures and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high input matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor between gate and drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this LNA is $0.202mm^2$, including pads. Measurement results illustrate that input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 7~8 dB over 1.5~13 GHz. In addition, good linearity(IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.12
• /
• pp.43-53
• /
• 2007

We have analyzed low current operation characteristics of a VCSEL transmitter operating at fixed Current over wide temperature range. Used 850 nm oxide VCSEL has low temperature dependence of the threshold current and $d^2I_{th}/dT^2$ is approximately $1.346\times10^{-4}mA/^{\circ}C^2$. We fixed on-current so that output power from the chip is 1 mW at $20^{\circ}C$ and investigated the turn-on, turn-off characteristics and eye-diagram of the 850 nm oxide VCSEL transmitter with varying ambient temperature and off-current. We measured rise time, fall time, extinction ratio and timing jitter by changing tile ambient temperature and off-current. With the fixed off-current of around $0.1\sim0.2mA$ lower than the lowest threshold current the transmitter successfully operated at 1.25 Gbps over a wide temperature range from $-20^{\circ}C$ to $80^{\circ}C$.

• Korean Chemical Engineering Research
• /
• v.51 no.2
• /
• pp.214-220
• /
• 2013

Hydrophobic coating on a silicate-based yellow phosphor ($Sr_2SiO_4:Eu^{2+}$) was carried out by using hexamethyldisiloxane (HMDSO) precursor in an atmospheric pressure dielectric barrier discharge plasma reactor, eventually to improve the long-term stability and reliability of the phosphor. The phosphor powder samples were characterized by a scanning electron microscope (SEM), a transmission electron microscope (TEM), a fluorescence spectrophotometer and a contact angle analyzer. After the coating was prepared, the contact angle of the phosphor powder increased to $133.0^{\circ}$ for water and to $140.5^{\circ}$ for glycerol, indicating that a hydrophobic layer was formed on its surface. The phosphor coated with HMDSO exhibited photoluminescence enhancement up to 7.8%. The SEM and TEM images of the phosphor powder revealed that the plasma coating led to a morphological change from grain-like structure to smooth surface with 31~46 nm thick hydrophobic layer. The light emitting diode (3528 1 chip LED) fabricated with the coated phosphor showed a substantial enhancement in the reliability under a special test condition at $85^{\circ}C$ and 85% relative humidity for 1,000 h (85/85 testing). The plasma-mediated method proposed in this work may be applicable to the formation of 3-dimensional coating layer on irregular-shaped phosphor powder, thereby improving the reliability.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.172-173
• /
• 2012

Currently GaN based LED is known to show high internal or external efficiency at low current range. However, this LED operation occurs at high current range and in this range, a significant performance degradation known as 'efficiency droop' occurs. Auger process, carrier leakage process, field effect due to lattice mismatch and thermal effects have been discussed as the causes of loss of efficiency, and these phenomena are major hindrance in LED performance. In order to investigate the main effects of efficiency loss and overcome such effects, it is essential to obtain relative proportion of measurements of internal quantum efficiency (IQE) and various radiative and nonradiative recombination processes. Also, it is very important to obtain radiative and non-radiative recombination times in LEDs. In this research, we measured the IQE of InGaN/GaN multiple quantum wells (MQWs) LEDs with PSS and Planar substrate using modified ABC equation, and investigated the physical mechanism behind by analyzing the emission energy, full-width half maximum (FWHM) of the emission spectra, and carrier recombination dynamic by time-resolved electroluminescence (TREL) measurement using pulse current generator. The LED layer structures were grown on a c-plane sapphire substrate and the active region consists of five 30 ${\AA}$ thick In0.15Ga0.85N QWs. The dimension of the fabricated LED chip was $800um{\times}300um$. Fig. 1. is shown external quantum efficiency (EQE) of both samples. Peak efficiency of LED with PSS is 92% and peak efficiency of LED with planar substrate is 82%. We also confirm that droop of PSS sample is slightly larger than planar substrate sample. Fig. 2 is shown that analysis of relation between IQE and decay time with increasing current using TREL method.

• Asian-Australasian Journal of Animal Sciences
• /
• v.31 no.6
• /
• pp.784-790
• /
• 2018

Objective: The genetic effects of an individual on the phenotypes of its social partners, such as its pen mates, are known as social genetic effects. This study aims to identify the candidate genes for social (pen-mates') average daily gain (ADG) in pigs by using the genome-wide association approach. Methods: Social ADG (sADG) was the average ADG of unrelated pen-mates (strangers). We used the phenotype data (16,802 records) after correcting for batch (week), sex, pen, number of strangers (1 to 7 pigs) in the pen, full-sib rate (0% to 80%) within pen, and age at the end of the test. A total of 1,041 pigs from Landrace breeds were genotyped using the Illumina PorcineSNP60 v2 BeadChip panel, which comprised 61,565 single nucleotide polymorphism (SNP) markers. After quality control, 909 individuals and 39,837 markers remained for sADG in genome-wide association study. Results: We detected five new SNPs, all on chromosome 6, which have not been associated with social ADG or other growth traits to date. One SNP was inside the prostaglandin $F2{\alpha}$ receptor (PTGFR) gene, another SNP was located 22 kb upstream of gene interferon-induced protein 44 (IFI44), and the last three SNPs were between 161 kb and 191 kb upstream of the EGF latrophilin and seven transmembrane domain-containing protein 1 (ELTD1) gene. PTGFR, IFI44, and ELTD1 were never associated with social interaction and social genetic effects in any of the previous studies. Conclusion: The identification of several genomic regions, and candidate genes associated with social genetic effects reported here, could contribute to a better understanding of the genetic basis of interaction traits for ADG. In conclusion, we suggest that the PTGFR, IFI44, and ELTD1 may be used as a molecular marker for sADG, although their functional effect was not defined yet. Thus, it will be of interest to execute association studies in those genes.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.11
• /
• pp.9-16
• /
• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.40 no.11
• /
• pp.51-62
• /
• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.12 s.354
• /
• pp.15-22
• /
• 2006

In this paper, 1.8V 8-bit 500MSPS Low-power CMOS Digital-to-Analog Converter(DAC) for UWB(Ultra Wide Band) Communication Systeme is proposed. The architecture of the DAC is based on a current steering 6+2 full matrix type which has low glitch and high linearity. In order to achieve a high speed and good performance, a current cell with a high output impedance and wide swing output range is designed. Further a thermometer decoder with same delay time and low-power switching decoder for high efficiency performance are proposed. The proposed DAC was implemented with TSMC 0.18um 1-poly 6-metal N-well CMOS technology. The measured SFDR was 49dB when the output frequency was 50MHz at 500MS/s sampling frequency. The measured INL and DNL were 0.9LSB and 0.3LSB respectively. The DAC power dissipation was 20mW and the effective chip area was $0.63mm^2$.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.5
• /
• pp.51-57
• /
• 2015

In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.53 no.8
• /
• pp.113-118
• /
• 2016

In this paper, a read-in integrated circuit (RIIC) for IR scene projectors (IRSPs) adopting a sub-frame control technique is proposed, which minimizes the reduction of the apparent temperature of the IR images projected from IRSPs operating at a frame rate of 30 Hz. The proposed sub-frame control technique significantly reduces the amount of scene data loss on capacitors, which is caused by leakage currents flowing through MOSFET switches during holding periods, by dividing a unit frame into 8 sub-frames and refreshing the same scene data for each sub-frame. A current-drive RIIC was designed for the higher apparent temperature of IR radiated from the emitter, and it receives the scene data as a form of analog voltages from an external DAC. A prototype chip with a $64{\times}32$ RIIC array was fabricated using Magnachip/SKhynix $0.35{\mu}m$ 2-poly 4-metal CMOS process, and the measured maximum output data current is $230.3{\mu}A$. This amount of current ensures the projection of IR images whose maximum apparent temperature is $366.2^{\circ}C$ in the mid-wavelength IR (MWIR) when applied to a prototype emitter having a resistance of $15k{\Omega}$.