• Title/Summary/Keyword: CHIP

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Effect of Physical Characteristics of Emulsion Asphalt and Aggregate on Performance of Chip Seal Pavements (유화아스팔트 바인더와 골재 특성이 칩씰 포장의 공용성에 미치는 영향 연구)

  • Hong, Ki Yun;Kim, Tae Woo;Lee, Hyun Jong;Park, Hee Mun;Ham, Sang Min
    • International Journal of Highway Engineering
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    • v.15 no.2
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    • pp.65-71
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    • 2013
  • PURPOSES : The objective of this study is to evaluate the effect of physical characteristics of emulsion asphalt and aggregate on performance of chip seal pavements. METHODS : In order to evaluate the performance of chip seal materials, the sweep tests and Vialit Plate Shock tests were conducted on the mixtures with five emulsion asphalt binders and three aggregate types. The sweep tests was intended to investigate the change of bonding properties between emulsion asphalt and aggregate with curing time. The Vialit Plate Shock test was used to evaluate the bonding properties of chip seal materials at low temperatures. RESULTS : Results from sweep tests showed that polymer modified emulsion asphalt can reduce the curing time by 1.5 hour comparing with typical emulsion asphalt. It is also found that the Flakiness Index of aggregates and absorption rate of binder are the major factors affecting the bonding properties of chip seal materials. The Vialit Plate Shock test results showed that the average aggregate loss of CRS-2 is ten times higher than CRS-2P No.2 indicating that the use of polymer additives in emulsion asphalt can improve the performance of chip seal materials in low temperature region. CONCLUSIONS : The use of polymer in emulsion asphalt can decrease the curing time of chip seal materials and increase the bonding properties between aggregates and asphalt binder. It is also concluded that the lower Flakiness Index and absorption rate of aggregates can improve the performance of chip seal pavement.

Comparison of Clinical Efficacy between an HPV DNA Chip and a Hybrid-Capture II Assay in a Patient with Abnormal Colposcopic Findings (질 확대경상 비정상 소견을 보인 환자에서 HPV DNA chip과 Hybrid-Capture II assay의 임상적 유용성 비교)

  • Kim, Tae-Jung;Jung, Chan-Kwon;Lee, Ah-Won;Jung, Eun-Sun;Choi, Young-Jin;Lee, Kyo-Young;Park, Jong-Sup
    • The Korean Journal of Cytopathology
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    • v.19 no.2
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    • pp.119-125
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    • 2008
  • This study was performed to compare the efficacy between a DNA chip method and a Hybrid-Capture II assay (HC-II) for detecting human papillomavirus in patients with intraepithelial lesions of the uterine cervix. From May, 2005, to June, 2006, 192 patients with abnormal colposcopic findings received cervical cytology, HC-II and HPV DNA chip tests, and colposcopic biopsy or conization. We compared the results of HC-II and HPV DNA chip in conjunction with liquid based cervical cytology (LBCC) and confirmed the results of biopsy or conization. The sensitivity of the HPV DNA chip test was higher than HC-II or LBCC. The HPV DNA chip in conjunction with LBCC showed higher sensitivity than any single method and higher sensitivity than HC-II with LBCC. We confirmed that the HPV DNA chip test was more sensitive for detecting HPV in cervical lesions than HC-II, and that it would provide more useful clinical information about HPV type and its multiple infections.

Development of a High speed Actuator for electric performance testing System of ceramic chips (세라믹칩 전기적 성능검사 시스템을 위한 고속구동 액튜에이터 개발)

  • Bae, Jin-Ho;Kim, Sung-Gaun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.4
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    • pp.1509-1514
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    • 2011
  • The core of IT products, electronic components, especially the MLCC, chip inductors, chip Varistors and so on. In order to test the electrical characteristics of the chip using the Reno-pin contact test method has been used. In current chips, mass production of semiconductor manufacturing processes, high-speed production test for the chip speed up, precision is required. But Vibration displacement is a very short, so in order to overcome these shortcomings, the displacement amplification to design the structure has been actively studied. In this paper, a building structure with a flexible hinge was designed amplification instrument, semiconductor chip industry in the performance test and inspection equipment to measure the electrical characteristics of high speed linear actuators Reno-Pin using system was developed.

Flip Chip Process on the Local Stiffness-variant Stretchable Substrate for Stretchable Electronic Packages (신축성 전자패키지용 강성도 국부변환 신축기판에서의 플립칩 공정)

  • Park, Donghyeun;Oh, Tae Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.25 no.4
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    • pp.155-161
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    • 2018
  • A Si chip with the Cu/Au bumps of $100-{\mu}m$ diameter was flip-chip bonded using different anisotropic conductive adhesives (ACAs) onto the local stiffness-variant stretchable substrate consisting of polydimethylsiloxane (PDMS) and flexible printed circuit board (FPCB). The average contact resistances of the flip-chip joints processed with ACAs containing different conductive particles were evaluated and compared. The specimen, which was flip-chip bonded using the ACA with Au-coated polymer balls as conductive particles, exhibited a contact resistance of $43.2m{\Omega}$. The contact resistance of the Si chip, which was flip-chip processed with the ACA containing SnBi solder particles, was measured as $36.2m{\Omega}$, On the contrary, an electric open occurred for the sample bonded using the ACA with Ni particles, which was attributed to the formation of flip-chip joints without any entrapped Ni particles because of the least amount of Ni particles in the ACA.

Evaluation of Properties of Mortar and Concrete using Wood Chip Cogeneration Plant Flooring as Fine Aggregate (목재칩 열병합 발전소 바닥재를 잔골재로 활용한 모르타르 및 콘크리트 특성 평가)

  • Kang, Suk-Pyo;Hong, Seong-Uk
    • Journal of the Korean Recycled Construction Resources Institute
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    • v.10 no.3
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    • pp.327-334
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    • 2022
  • In this study, in order to evaluate the characteristics of mortar and concrete using wood chip cogeneration plant flooring as fine aggregate, mortar characteristics according to wood chip aggregate replacement rate and water-cement ratio as a substitute for crushed sand, and concrete characteristics according to wood chip aggregate replacement rate were compared and evaluated. The cement mortar flow according to the wood chip aggregate replacement rate showed a tendency to increase as the wood chip aggregate replacement rate increased, and the compressive strength and flexural strength increased as the wood chip aggregate replacement rate increased. The slump and air content of concrete increased as the aggregate replacement rate increased, and the compressive strength and tensile splitting strength of concrete tended to increase as the wood chip aggregate replacement rate increased. Accordingly, the possibility of using the flooring by the cogeneration plant as a fine aggregate for concrete was confirmed.

A Low Power Analog CMOS Vision Chip for Edge Detection Using Electronic Switches

  • Kim, Jung-Hwan;Kong, Jae-Sung;Suh, Sung-Ho;Lee, Min-Ho;Shin, Jang-Kyoo;Park, Hong-Bae;Choi, Chang-Auck
    • ETRI Journal
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    • v.27 no.5
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    • pp.539-544
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    • 2005
  • An analog CMOS vision chip for edge detection with power consumption below 20mW was designed by adopting electronic switches. An electronic switch separates the edge detection circuit into two parts; one is a logarithmic compression photocircuit, the other is a signal processing circuit for edge detection. The electronic switch controls the connection between the two circuits. When the electronic switch is OFF, it can intercept the current flow through the signal processing circuit and restrict the magnitude of the current flow below several hundred nA. The estimated power consumption of the chip, with $128{\times}128$ pixels, was below 20mW. The vision chip was designed using $0.25{\mu}m$ 1-poly 5-metal standard full custom CMOS process technology.

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An S-Band Multifunction Chip with a Simple Interface for Active Phased Array Base Station Antennas

  • Jeong, Jin-Cheol;Shin, Donghwan;Ju, Inkwon;Yom, In-Bok
    • ETRI Journal
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    • v.35 no.3
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    • pp.378-385
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    • 2013
  • An S-band multifunction chip with a simple interface for an active phased array base station antenna for next-generation mobile communications is designed and fabricated using commercial 0.5-${\mu}m$ GaAs pHEMT technology. To reduce the cost of the module assembly and to reduce the number of chip interfaces for a compact transmit/receive module, a digital serial-to-parallel converter and an active bias circuit are integrated into the designed chip. The chip can be controlled and driven using only five interfaces. With 6-bit phase shifting and 6-bit attenuation, it provides a wideband performance employing a shunt-feedback technique for amplifiers. With a compact size of 16 $mm^2$ ($4mm{\times}4mm$), the proposed chip exhibits a gain of 26 dB, a P1dB of 12 dBm, and a noise figure of 3.5 dB over a wide frequency range of 1.8 GHz to 3.2 GHz.

Study on the Composting of Swine Manure using Wood Chip as a Bulking Agent (목편을 이용한 돈분 퇴비화에 관한 연구)

  • 김형호;박치호;김태일;정광화;최희철;이덕수;한정대
    • Journal of Animal Environmental Science
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    • v.3 no.1
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    • pp.27-34
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    • 1997
  • This study was carried out to evaluate the feasibility of composting of swine manure with wood chips as a bulking agent. To evaluate the optimum blending ratio of wood chip to swine manure three levels of wood chip such as 100, 150, and 200% were blended on a volume basis with 100% of swine manure was used to determine the effect of wood chip compared with sawdust as a bulking agent on composting. The maximum temperature reached during composting was 70, 58, 48, 72$^{\circ}C$ at blending ratio of 100, 150, 200, and 50WC+50SD%, respectively. The bulk density of compost was increased extremely with increasing the blending level of wood chip. The C/N ratio of final compost ranged from 18.25 to 19.82 . Heavy metal contents in the final compost were in the range of 0.05∼0.16 mg/kg, 5,86∼10.95 $\mu\textrm{g}$/kg, and 295∼440 mg/kg for Cd, Hg, and Cu, respectively. It was concluded that the blending ratio of 200:100 of wood chip and manure by volume was satisfactory for swine manure composting.

A 77 GHz mHEMT MMIC Chip Set for Automotive Radar Systems

  • Kang, Dong-Min;Hong, Ju-Yeon;Shim, Jae-Yeob;Lee, Jin-Hee;Yoon, Hyung-Sup;Lee, Kyung-Ho
    • ETRI Journal
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    • v.27 no.2
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    • pp.133-139
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    • 2005
  • A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 ${\mu}$ gate-length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4-inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2mm${\times}$ 2mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1mm${\times}$ 2mm. The frequency doubler achieved an output power of -6 dBm at 76.5 GHz with a conversion gain of -16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2mm ${\times}$ 1.2mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W-band.

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Design of a Dingle-chip Multiprocessor with On-chip Learning for Large Scale Neural Network Simulation (대규모 신경망 시뮬레이션을 위한 칩상 학습가능한 단일칩 다중 프로세서의 구현)

  • 김종문;송윤선;김명원
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.2
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    • pp.149-158
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    • 1996
  • In this paper we describe designing and implementing a digital neural chip and a parallel neural machine for simulating large scale neural netsorks. The chip is a single-chip multiprocessor which has four digiral neural processors (DNP-II) of the same architecture. Each DNP-II has program memory and data memory, and the chip operates in MIMD (multi-instruction, multi-data) parallel processor. The DNP-II has the instruction set tailored to neural computation. Which can be sed to effectively simulate various neural network models including on-chip learning. The DNP-II facilitates four-way data-driven communication supporting the extensibility of parallel systems. The parallel neural machine consists of a host computer, processor boards, a buffer board and an interface board. Each processor board consists of 8*8 array of DNP-II(equivalently 2*2 neural chips). Each processor board acn be built including linear array, 2-D mesh and 2-D torus. This flexibility supports efficiency of mapping from neural network models into parallel strucgure. The neural system accomplishes the performance of maximum 40 GCPS(giga connection per second) with 16 processor boards.

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