• 전기학회논문지
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• 제58권1호
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• pp.107-112
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• 2009

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.

• 대한기계학회논문집
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• 제17권11호
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• pp.2664-2675
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• 1993

In this paper, the effects of chip breaker configuration on cutting forces for various cutting conditions are investigated and a method for predicting cutting forces effectively for chip breaker insert in milling is described. Based on the shear plane model and the relevant equations already existing for the relation among the parameters, the method makes use of the analytic geometric approach considering the configuration of cutting too by a 3-dimensional coordinate transformation matrix. The groove type chip breaker insert is modeled to be a double rake insert, represented by the first radial rake angle, the second radial rake angle and the length of land, and the program analyzing the cutting forces is developed. The program capability is verified by comparing the results with the experimental ones for a single cutter; and in case of primary cutting forces, the results of simulation and experiments agree very well showing 2%~16.7% difference within the feed rate range investigated.

• 대한기계학회논문집B
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• 제21권8호
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• pp.973-982
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• 1997

Effect of vortex generator on the heat transfer enhancement of electronic chips is investigated using naphthalene sublimation technique. Experiments are performed for a single chip and chip arrays, and shape of vortex generator, position of vortex generator, stream wise chip spacing and air velocity are varied. Local and average heat transfer coefficients are measured on the top surface of simulated electronic chips, and compared with those obtained without vortex generator. In case of a single chip, heat transfer augmentation is seen only on the upstream portion of chip surface, while heat transfer enhancement is found on the whole surface for chip arrays. Rectangular wing type vortex generator is found to be more effective than delta wing.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 추계학술대회
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• pp.1027-1032
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• 2003

Thermo-mechanical behavior of flip-chip plastic ball grid array (FC-PBGA) packages are characterized by high sensitive $Moir{\acute{e}}$ interferometry. $Moir{\acute{e}}$ fringe patterns are recorded and analyzed for several temperatures. Deformation analysis of bending displacements of the packages and average strains in the solder balls for a single-sided package assembly and a double-sided package assembly are presented. The bending displacement of the double-sided package assembly is smaller than that of the single-sided one. The largest of effective strain occurred in the solder ball located at the edge of the chip and its magnitude of the double-sided package assembly is greater than that of single-sided one.

• 한국정밀공학회지
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• 제31권6호
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• pp.521-525
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• 2014

Circulating tumor cells (CTCs) in the bloodstream of cancer patients provide an accessible source for detection, characterization, and monitoring of nonhematological cancers. The effectiveness of the CTC-Chip for the isolation of ovarian cancer cells was demonstrated by adapting the herringbone-chip (HB-Chip). The motions of the particles on the HB chip were simulated by a unique combination of buoyant, gravitational forces, and helical flows with a computational modeling. The motions of cells are demonstrated by applying polystylene bead and ovarian cancer cells into the microfabricated HB-Chip. The experimental results from beads and cells are well accordance with the simulated ones, as previously reported by Toner group. Thus, I expect that these modeling and experimental skills will play key roles in the clinical applications on CTC isolation as well as the basic research on characterization of CTCs under flow.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2005년도 춘계 학술대회
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• pp.79-83
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• 2005

IT 기술, 반도체 산업 등의 급격한 발전에 힘입어 최근의 첨단 전자, 통신제품은 초경량 초소형화와 동시에 고기능 복합화의 발전 추세를 보이고 있다. 이런 추세에 발맞추어 전자제품, 통신제품의 핵심적인 부품인 IC chip도 소형화되고 있다. IC chip 패키징 기술의 하나인 Filp Chip Package는 Module Substrate 위에 Chip Surface를 Bumping 시킴으로서 최단의 접속길이와 저열저항, 저유전율의 특성도 가지면서 초소형에 높은 수율의 저 원가생산성을 갖는 첨단의 패키징 기술이다. 이런 패키징 기술은 수요증가와 더불어 폭발적으로 늘어나고 있으나 까다로운 공정기술에 의해 아직 여러 회사에서 장비가 출시되고 있지 못한 상태이다. 이에 본 연구에서는 최근 수요가 증가하는 LCD Driver IC용 COF 장비를 위한 Flip chip Bonding 장비 및 시스템을 설계, 제작하였다.

• 전자공학회논문지B
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• 제30B권6호
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• pp.86-92
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• 1993

In this paper, we present a VLSI chip design of Multi-layer Bidirectionsl Associative Memory with good error-correction performance. The MBAM neural chip utilizes inner product implementation schems with binary storage and analog calculation.. Multi-layer can be constructed by direct cascading of these chips, and the number of neurons is expandable by parallel connection of these chips. We made proto-type chips and interface board to test the expansion. Currently the Chip has 32 input nodes, 32 output nodes, and can store up to 48 patterns, 32x48x2 SRAMs are included in the chip.

• Genomics & Informatics
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• 제9권2호
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• pp.89-91
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• 2011

DNA chips are becoming increasingly popular as a convenient way to perform vast amounts of experiments related to genes on a single chip. And the importance of analyzing the data that is provided by such DNA chips is becoming significant. A very important analysis on DNA chip data would be clustering genes to identify gene groups which have similar properties such as cancer. Clustering data for DNA chips usually deal with a large search space and has a very fuzzy characteristic. The Particle Swarm Optimization algorithm which was recently proposed is a very good candidate to solve such problems. In this paper, we propose a clustering mechanism that is based on the Particle Swarm Optimization algorithm. Our experiments show that the PSO-based clustering algorithm developed is efficient in terms of execution time for clustering DNA chip data, and thus be used to extract valuable information such as cancer related genes from DNA chip data with high cluster accuracy and in a timely manner.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제4권3호
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• pp.316-321
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• 2004

In this paper, we have developed a new mounting head system for flip chip. The proposed head system consists of a macro/micro positioning actuator for stable force control. The macro actuator provides the system with a gross motion while the micro device yields fine tuned motion to reduce the harmful impact force that occurs between very small sized electronic parts and the surface of a PCB(printed circuit board). In order to show the effectiveness of the proposed macro/micro chip mounting system, we compared the proposed system with the conventional chip mounting head equipped with a macro actuator only. A series of experiments were executed under the mounting conditions such as various access velocities and PCB stiffness. As a result of this study, a satisfactory voice coil actuator as the micro actuator has been developed, and its performance meet well the specifications desired for the design of the chip mounting head system and show good correspondence between theoretical analysis and experimental results.

• 한국정보통신학회논문지
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• 제1권2호
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• pp.193-197
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• 1997

In this paper, we propose a new PN chip clock generator which employs two synchronous counters to achieve precise phase control of chip clock. In a CDMA code acquisition and tracking system, the PN chip clock is required to operate highly reliable without any glitch even under harsh environment condition such as temperature and voltage fluctu-aliens. The digital implementation of the proposed PN chip clock generator imparts it with much desired reliability. Since the proposed chip clock generator can be easily controlled into one of the states: free running, phase advance, and delay state, it can be applied to data processing as well as code synchronization. We have done FPGA implementation of the proposed logic and have verified its satisfactory operation up to 50 MHz.