• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.498-501
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• 2002

In the process of Log-In to the system, clear User authentication is the beginning of the information protection service. In the open communication system of today, it is true that a password as security instrument and the inner mechanism of the system and cryptography algorithm for the support of this are also poor. For this reason, this dissertation had a final aim to design the user authentication system, which offer the accuracy and safety. It used RSA and CBC mode of DES as cryptography algorithm and used the Challenge-Response scheme at a authentication protocol and designed the User authentication system to which user access using one time password, output of token to guarantee the safety of the authentication protocol. Alto by using the Public key cryptography algorithm, it could embody the more safe User authentication system.

• Convergence Security Journal
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• v.11 no.3
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• pp.25-30
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• 2011

WEP is proposed networks dominate the market in the future wireless LAN encryption and authentication features to provide a secure protocol. However, WEP does not suggest a specific measures when generating the initial values used for the creation cipher text, the initial value problem because tile size and no-encryption if you have been raised about the safety issue. In this paper pointed out the vulnerabilities of WEP and the proposed improvement plan for this improvement was proposed based on the initial value to avoid re-creating the initial value of the system and using a block cipher in CBC mode for confidentiality and to provide mutual authentication New WLAN security model was proposed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.10
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• pp.1164-1174
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• 1992

In this paper, an Information Security protocol in LLC/MAC Layer Architecture is discussed. This paper examines the security Vulnerability and threats, the security Service required to protect these threats, and architectural considerations of security protocol in IEEE 802 LAN architecture. To provide an Information security service, an information security protocol(SP2 : Security Protocol 2) PDU construction with LLC/MAC service primitives is suggested. To construct the SP2 protocol, the ECB, CBC mode of DES algorithm and DAA(Data Authentication Algorithm) of FIPS is used. The SP2 protocol suggested in this paper provides data origin authentication, data confidentiality, data integrity service.

• Journal of Dental Rehabilitation and Applied Science
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• v.29 no.2
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• pp.163-173
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• 2013

When the mandible performs opening movement, the condyle-disk complex conducts sliding movement along the articular eminence. Thus, anatomic configuration of articular eminence is very important to normal movement of TMJ. The purpose of this study was to measure the posterior slope of the articular eminence and evaluate the effect of a pathologic bone change in the condylar head on the stiffness of articular eminence, and compare the differences of the articular eminence slope by gender and age using dental cone-beam CT. As using i-CAT Cone-Beam Computed Tomography, the CT images of 204 TMJs of 102 patients(43 men and 59 women, mean age: 37.7 years) who were diagnosed at Wonkwang University Sanbon Dental Hospital were evaluated. All images were converted into a TMJ analysis mode to observe the continuous sagittal section images and coronal section images of the joints. To observe and assess bone changes in the condyle, three dentists measured the stiffness of the articular eminence on the same images, and when two of the three dentists agreed on their reading, these results were adopted and recorded. The articular eminence slope, considering the condylar anatomic configuration, was measured in three regions, namely, lateral part, central part, and medial part of the condyle. In the cases of a normal condyle(NCBC) and a condyle(CBC) with bone change, the articular eminence slopes were $57.0^{\circ}$(NCBC) and $51.8^{\circ}$(CBC) at the medial part, $57.9^{\circ}$(NCBC) and $52.4^{\circ}$(CBC) at the central part, and $55.1^{\circ}$(NCBC) and $49.5^{\circ}$(CBC) at the lateral part of the condyle. And the articular eminence slope of the condyle with bone change demonstrated less steepness than that of normal condyle (p<0.05). The articular eminence slope showed mediolaterally that it was the steepest at the central, followed by at the medial, and at the lateral (p<0.05). There were no significant differences by the gender and the age (p.0.05).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.798-803
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.1li wireless LAN security. To maximize its performance, two AES cores ate used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining) mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about $20\%$ compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 13,360 gates, and the estimated throughput is about 168 Mbps at 54-MHz clock frequency. The functionality of the CCMP core is verified by Excalibur SoC implementation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.367-370
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.11i wireless LAN security. To maximize its performance, two AES cores are used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining)mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about 25% compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 15,450 gates, and the estimated throughput is about 128 Mbps at 50-MHz clock frequency). The functionality of the CCMP core is verified by Excalibur SoC implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.5
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• pp.15-25
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• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.285-287
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• 1999

블록 암호알고리즘에 대한 기존의 연산 모드들(ECB 또는 CBC 등)은, 각 블록에 대하여 동일한 키로 암호화를 수행한다. 이것은 침입자가 한번의 암호 요청만을 수행하여 많은 수의 평문/암호문 쌍을 얻을 수 있게 함으로써 차분해독법 등의 공격에는 안전성을 제공하지 않는다. 본 논문에서는 블록 암호 알고리즘을 위한 새로운 모드를 제안하는데, 이 모드에서는 암호화되는 각각의 블록이 서로 다른 키로 암호화되도록 함으로써 블록의 개수가 많아짐에 따라 안전성 면에서 상당한 이득을 얻게 된다. 각 블록을 위한 서로 다른 키를 생성하는 것이 추가 연산을 필요로 하지만, 제안하는 모드를 DES에 적용한 TDK(a mode for DEA with unTraceable Dynamic Keys)의 수행 시간을 pentium과 sun sparc 상에서 측정해 본 결과 ECB 모드와 거의 유사함을 알 수 있었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.