• Journal of Broadcast Engineering
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• v.14 no.5
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• pp.551-560
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• 2009

This paper proposes a method for efficient lossless depth map coding for MPEG 3D-Video coding. In general, the conventional video coding method such as H.264 has been used for depth map coding. However, the conventional video coding methods do not consider the image characteristics of the depth map. Therefore, as a lossless depth map coding method, this paper proposes a bit-plane based lossless depth mar coding method by using the MPEG-4 Part 2 shape coding scheme. Simulation results show that the proposed method achieves the compression ratios of 28.91:1. In intra-only coding, proposed method reduces the bitrate by 24.84% in comparison with the JPEG-LS scheme, by 39.35% in comparison with the JPEG-2000 scheme, by 30.30% in comparison with the H.264(CAVLC mode) scheme, and by 16.65% in comparison with the H.264(CABAC mode) scheme. In addition, in intra and inter coding the proposed method reduces the bitrate by 36.22% in comparison with the H.264(CAVLC mode) scheme, and by 23.71% in comparison with the 0.264(CABAC mode) scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2285-2291
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• 2011

In this paper, H.264 high profile intra frame encoder, which integrates intra prediction, context-based adaptive variable length coding(CAVLC), and DDR2 memory control module, is proposed. The designed encoder can be operated in 440 cycle for one-macroblock. In order to verify the encoder function, we developed the reference C from JM 13.2 and verified the developed hardware using test vector generated by reference C. The designed encoder is verified in the FPGA (field programmable gate array) with operating frequency of 200 MHz for DMA (direct memory access), operating frequency of 50 MHz of Encoder module, and 25 MHz for VIM(video input module). The number of LUT is 43099, which is about 20 % of Virtex 5 XC5VLX330.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.61-68
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• 2008

In this paper, we propose an efficient hardware architecture and algorithm to increase an encoding process rate and implement a hardware for CABAC (Context Adaptive Binary Arithmetic Coding) which is used with one of the entropy coding ways for the latest video compression technique, H.264/AVC (Advanced Video Coding). CABAC typically provides a better high compression performance maximum 15% compared with CAVLC. However, the complexity of operation of CABAC is significantly higher than the CAVLC. Because of complicated data dependency during the encoding process, the complexity of operation is higher. Therefore, various architectures were proposed to reduce an amount of operation. However, they have still latency on account of complicated data dependency. The proposed architecture has two techniques to implement efficient pipeline architecture. The one is quick calculation of 7, 8th bits used to calculate a probability is the first step in Binary arithmetic coding. The other is one step reduced pipeline arcbitecture when the type of the encoded symbols is MPS. By adopting these two techniques, the required processing time was reduced about 27-29% compared with previous architectures. It is designed in a hardware description language and total logic gate count is 19K using 0.18um standard cell library.

• Journal of Advanced Navigation Technology
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• v.18 no.6
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• pp.600-608
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• 2014

In this paper, CABAC H/W module is developed using co-design method. After entire H.264/AVC encoder was developed with C using reference SW(JM), CABAC H/W IP is developed as a block in H.264/AVC encoder. Context modeller of CABAC is included on the hardware to update the changed value during binary encoding, which enables the efficient usage of memory and the efficient design of I/O stream. Hardware IP is co-operated with the reference software JM of H.264/AVC, and executed on Virtex-4 FX60 FPGA on ML410 board. Functional simulation is done using Modelsim. Compared with existing H/W module of CABAC with register-level design, the development time is reduced greatly and software engineer can design H/W module more easily. As a result, the used amount of slice in CABAC is less than 1/3 of that of CAVLC module. The proposed co-design method is useful to provide hardware accelerator in need of speed-up of high efficient video encoder in embedded system.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.5 s.305
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• pp.115-122
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• 2005

There are some problems in directly applying the conventional MPEG bit-stream based watermarking schemes to the bit-stream of a new compression standard, H.264/AVC. In this paper we analyze the effects of the conventional DCT-based watermarking scheme to H.264/AVC, especially in terms of image distortions and bit-rate changes. It turns out that the intra-frame prediction md CAVLC of H.264/AVC with the watermarking worsen the image distortions and bit-rate changes. The experiment results show on average 28.17dB decrease in PSNR and 56.71% increase in bit-rate over all QPs.

• Journal of Broadcast Engineering
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• v.13 no.5
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• pp.732-743
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• 2008

In H.264/AVC, 4$\times$4 block transform is used for intra and inter prediction instead of 8$\times$8 block transform. Using small block size coding, H.264/AVC obtains high temporal prediction efficiency, however, it has limitation in utilizing spatial redundancy. Motivated on these points, we propose a multi-dimensional transform which achieves both the accuracy of temporal prediction as well as effective use of spatial redundancy. From preliminary experiments, the proposed multi-dimensional transform achieves higher energy compaction than 2-D DCT used in H.264. We designed an integer-based transform and quantization coder for multi-dimensional coder. Moreover, several additional methods for multi-dimensional coder are proposed, which are cube forming, scan order, mode decision and updating parameters. The Context-based Adaptive Variable-Length Coding (CAVLC) used in H.264 was employed for the entropy coder. Simulation results show that the performance of the multi-dimensional codec appears similar to that of H.264 in lower bit rates although the rate-distortion curves of the multi-dimensional DCT measured by entropy and the number of non-zero coefficients show remarkably higher performance than those of H.264/AVC. This implies that more efficient entropy coder optimized to the statistics of multi-dimensional DCT coefficients and rate-distortion operation are needed to take full advantage of the multi-dimensional DCT. There remains many issues and future works about multi-dimensional coder to improve coding efficiency over H.264/AVC.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.946-948
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• 2005

H.264/AVC는 SoC/IEC MPEG와 ITU-T Video Coding Experts Group에서 함께 발표한 비디오 코딩을 위한 가장 최근의 표준이다. 기존의 표준들 보다 적은 비트로 높은 압축률과 좋은 화질을 제공하고 있다. 그러나 1/4 화소 움직임 예측과 보상의 지원과 7가지의 가변블록에 대한 움직임예측과 블록모드별 RD(Rate-Distortion)를 수행하고 CAVLC등 H.264/AVC 표준에서 채택한 여러 가지 비디오 압축방식으로 인해 그 복잡도가 훨씬 증가하였다. 이 논문에서 H.264/AVC의 복호화기에서 복잡도의 약 $40\%$ 이상을 차지하는 움직임보상 모듈을 효율적으로 수행하고 최적화하기 위한 방법을 제안한다. 예측된 모션벡터에 따라 창조하는 프레임에서 매크로블록을 만들어 내는 움직임 보상 과정을 수행하는 데 있어서 접근 지연시간이 큰 외부 메모리 창조를 선인출 메커니즘을 이용하여 미리 예측하여 수행함으로써 전체 수행시간을 줄이는 기법을 적용하였다. 이를 통하여 가변길이 복호화 모듈과 움직임 보상모듈을 수정하여 반복적으로 읽고, 쓰기를 수행해야 하는 횟수를 줄였다. 실험 결과 본 논문에서 제안하는 방법을 이용하여 복호화 과정을 수행했을 때 PSNR(Peak Signal to Noise Ratio)의 손실은 전혀 없으면서 복호화기의 전체 실행시간을 약 $5\%$ 향상시키고, 핵심 모듈인 움직임 보상과정에서 약 $20\%$ 정도 실행시간을 향상시키는 등 높은 성능 향상을 보였다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.11a
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• pp.161-164
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• 2013

본 논문에서는 다양한 멀티미디어 코덱을 고속으로 처리하기 위하여 전용하드웨어가 아닌 병렬 어레이 프로세서 기반의 U-Chip(Universal-Chip) 구조를 제안하고 TSMC 80nm 공정을 사용하여 11,865,090개의 게이트 수를 가지는 칩으로 개발하였다. U-Chip은 역양자화(IQ), 역변환(IT), 움직임 보상(MC) 연산을 위한 $4{\times}16$ 개의 프로세싱 유닛으로 구성된 병렬 어레이 프로세서와 문맥적응적 가변길이디코딩(CAVLC)을 위한 비트스트림 프로세서와 인트라 예측(IP), 디블록킹필터(DF) 연산을 위한 순차 프로세서와 DMAC의 데이터 전송 및 각 프로세서를 제어하여 병렬 파이프라인 스케쥴링을 처리하는 시퀀서 프로세서 등으로 구성된다. 1개의 프로세싱 유닛에 1개의 매크로블록 데이터를 맵핑하여 총 64개의 매크로블록을 병렬처리 하였다. 64개 매크로블록의 대용량 데이터 전송 시간과 각 프로세서들의 연산을 동시에 병렬 파이프라인 함으로서 전체 연산 성능을 높일 수 있는 이점이 있다. 병렬 파이프라인 구조의 H.264 디코더 프로그램을 개발하였고 제작된 U-Chip을 통해 $720{\times}480$ 크기의 베이스라인 프로파일 영상에 대하여 코어 192MHz 동작, DDR 메모리 96MHz 동작에서 30fps의 처리율을 가짐을 확인하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.11
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• pp.2020-2025
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• 2006

H.264/AVC is newest video coding standard of the ITU-T Video coding Experts Group and the ISO/IEC Moving Picture Expets Group. Recently H.264/AVC has been adopted as a video compression standard in DMB and multimedia equipments. In this paper, we propose a H.264/AVC intra frame decoder which can minimize the memory usage and chip size. The proposed intra frame decoder is described in VHDL language and simulated in model_sim. It was verified in chip level by downloading to XCV1000E FPGA chip.