• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.249-255
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• 2007

In general, a large amount of the memory accesses are required for the CAVLC decoding in H.264/AVC. It is a serious problem for the applications such as a DMB and videophone services because the considerable power is consumed for accessing the memory. In order to solve this problem, we propose an efficient decoding method for the coeff-token which is one of the syntax elements of CAVLC. In this paper, the variable length code table is re-designed with the new codewords which are defined by investigating the architecture of the conventional codeword for the coeff_token element. A new coeff_token decoding method is developed based on the suggested table. The simulation results show that the proposed algorithm achieves an approximately 85% memory access saving without video-quality degradation, compared to the conventional CAVLC decoding.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.237-240
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• 2005

This paper propose an novel CAVLC architcture for H.264 and designed the CAVLC module which can be used in AMBA based design. This designed module can be operated in 420 cycle for one-macroblock and support both long-start code method using Annex B.1 and RTP. To verify the CAVLC architecture, we developed the reference C from JM8.5 and verified the our developed hardware using test vector generated by reference C. The designed circuit can be operated in 54MHz clock system, and has 14096 gate counts using Hynix 0.35 um TLM process.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.2
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• pp.26-32
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• 2008

Video compression schemes have been developed and used for many years. Currently, H.264/AVC is the most efficient video coding standard. The H.264/AVC baseline profile adopts CAVLC(Context-Adaptive Variable Length Coding) method as an entropy coding method. CAVLC gives better performance in compression ratios than conventional VLC(Variable Length Coding). However, because CAVLC decoder uses a lot of VLC tables, the CAVLC decoder requires a lot of area in terms of hardware. Conversely, since it must look up the VLC tables, it gives a worse performance in terms of software. In this paper, we propose a new hierarchical grouping method for the VLC tables. We can obtain an index of codes in the reconstructed VLC tables by simple arithmetic operations. In this method, the VLC tables are accessed just once in decoding a symbol. We modeled the proposed algorithm in C language, compiled under ARM ADS1.2 and simulated it with Armulator. Experimental results show that the proposed algorithm reduces execution time by about 80% and 15% compared with the H.264/AVC reference program JM(Joint Model) 10.2 and the arithmetic operation algorithm which is recently proposed, respectively.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.4 s.316
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• pp.51-59
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) decoding which used for baseline profile and extended profile. Previous CAVLC architectures are consisted of five step block and each block gets effective bits from Controller block and Accumulator. If large number of non-zero coefficients exist, process for getting effective bits has to iterates many times. In order to reduce this unnecessary process, we propose two techniques, which combine five steps into four steps and reduce process to get efficiency bit by skipping addition step. By adopting these two techniques, the required processing time was reduced about 26% compared with previous architectures. It was designed in a hardware description language and total logic gate count was 16.83k using 0.18um standard cell library.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.6
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• pp.1104-1114
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• 2007

Digital video compression technique has played an important role that enables efficient transmission and storage of multimedia data where bandwidth and storage space are limited. The new video coding standard, H.264/AVC, developed by Joint Video Team(JVT) significantly outperforms previous standards in compression performance. Especially, variable length code(VLC) plays a crucial pun in video and image compression applications. H.264/AVC standard adopted Context-based Adaptive Variable Length Coding(CAVLC) as the entropy coding method. CAVLC of H.264/AVC requires a large number of the memory accesses. This is a serious problem for applications such as DMB and video phone service because of the considerable amount of power that is consumed in accessing the memory. In order to overcome this problem in this paper, we propose a variable length technique that implements memory-free coeff_token, level, and run_before decoding based on arithmetic operations and using only 70% of the required memory at total_zero variable length decoding.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.552-555
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• 2007

지상파 DMB등에서 많이 사용하고 있는 기술은 H.264이다. 이 H.264는 적은 비트율에 비하여 고해상도의 영상을 만들어 낸다. 이런 손실압축을 하기 위해서 인트라와 인터등과 같은 전처리 과정과 DCT(Discrete Cosine Transform), 양자화 등등이 존재하지만 H.264에서 실제로 압축이 되는 부분은 엔트로피코딩이다. H.264에서는 Exp-Golomb과 CAVLC(Context-Adaptive Variable Length Coding), CABAC(Context-Adaptive Binary Arithmetic Coding) 세 가지를 지원하고 있다. 이중 CAVLC는 테이블을 기반으로한 압축기법을 사용한다. 테이블을 이용할 때는 코드워드의 길이와 값을 비교하는 방식을 사용하게 된다. 이는 수 많은 메모리 접속으로 인한 전력소모와 연산지연을 가져온다. 본 논문에서는 전송된 비트스트림에서 데이터를 찾을 때 코드워드의 길이와 값을 테이블에 비교해서 찾지 않고 테이블에 존재하는 규칙을 수식화 하여 찾을 수 있도록 하였다. 이는 최초 '1'이 나올때까지의 '0'의 개수와 그 이후 존재하는 코드의 값을 이용하여서 각 단계에 필요한 데이터를 추출해 낸다. 위와 같은 알고리즘을 이용하여 VHDL언어로 설계하였다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.791-792
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• 2008

We present a new algorithm for VLC table prediction in H.264 context-based adaptive variable length coding (CAVLC). Using both the correlation of coding modes and the statistics of the mode distribution in intra and inter frames, we can predict an appropriate VLC table of the given $4{\times}4$ block. Experimental results demonstrate that the proposed algorithm reduces the bit rate about 0.97% on average, compared to the H.264/AVC standard.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.464-468
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• 2008

본 논문은, H,264/AVC 비디오 코덱의 저전력용 CAVLC 디코더를 위한 coeff_token 회로의 면적을 최적화 한 설계를 제시한다. CAVLC 디코더의 전력 소비를 줄이기 위해서 coeff_token 회로에서의 메모리 참조 빈도수를 줄이는 여러 가지 방법이 제안되어 왔다. 본 논문에서는 기존의 저전력용으로 개발된 coeff_token 회로 중 가장 전력 소비가 낮은 방식의 메모리 구조와 수식 계산 회로를 변형시켜서 전력 소비를 같은 수준으로 유지하면서도 면적을 더욱 줄이는 방법을 제안한다. 본 연구결과를 삼성 0.18 um 공정을 대상으로 합성한 결과 기존 방식에 비해서 1.1% 면적이 줄어드는 성과를 거두었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.371-381
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• 2005

In this paper, we propose an advanced hardware architecture for the CAVLC entropy encoder/decoder engine for real time video compression. The CAVLC (Context-based Adaptive Variable Length Coding) is a lossless compression method in H.264/AVC and it has high compression efficiency but has computational complexity. The reference memory size is optimized using partitioned storing method and memory reuse method which are based on partiality of memory referencing. We choose the hardware architecture which has the most suitable one in several encoder/decoder architectures for the mobile devices and improve its performance using parallel processing. The proposed architecture has been verified by ARM-interfaced emulation board using Altera Excalibur and also synthesized on Samsung 0.18 um CMOS technology. The synthesis result shows that the encoder can process about 300 CIF frames/s at 150MHz and the decoder can process about 250 CIF frames/s at 140Mhz. The hardware architectures are being used as core modules when implementing a complete H.264/AVC video encoder/decoder chip for real-time multimedia application.