• Title/Summary/Keyword: C.V.A.

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A NOTE ON CONNECTEDNESS IM KLEINEN IN C(X)

  • BAIK, BONG SHIN;RHEE, CHOON JAI
    • The Pure and Applied Mathematics
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    • v.22 no.2
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    • pp.139-144
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    • 2015
  • Abstract. In this paper, we investigate the relationships between the space X and the hyperspace C(X) concerning admissibility and connectedness im kleinen. The following results are obtained: Let X be a Hausdorff continuum, and let A ∈ C(X). (1) If for each open set U containing A there is a continuum K and a neighborhood V of a point of A such that V ⊂ IntK ⊂ K ⊂ U, then C(X) is connected im kleinen. at A. (2) If IntA ≠ ø, then for each open set U containing A there is a continuum K and a neighborhood V of a point of A such that V ⊂ IntK ⊂ K ⊂ U. (3) If X is connected im kleinen. at A, then A is admissible. (4) If A is admissible, then for any open subset U of C(X) containing A, there is an open subset V of X such that A ⊂ V ⊂ ∪U. (5) If for any open subset U of C(X) containing A, there is a subcontinuum K of X such that A ∈ IntK ⊂ K ⊂ U and there is an open subset V of X such that A ⊂ V ⊂ ∪ IntK, then A is admissible.

A Simulation Study on the Structural Optimization of a 800 V 4H-SiC Power DMOSFET (800 V급 4H-SiC DMOSFET 전력 소자 구조 최적화 시뮬레이션)

  • Choi, Chang-Yong;Kang, Min-Seok;Bahng, Wook;Kim, Sang-Cheol;Kim, Nam-Kyun;Koo, Sang-Mo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.22 no.8
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    • pp.637-640
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    • 2009
  • In this work, we demonstrate 800 V 4H-SiC power DMOSFETs with several structural alterations to obtain a low threshold voltage ($V_{TH}$) and a high figure of merit ($V_B\;^2/R_{SP,ON}$), To optimize the device performance, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. These parameters are optimized using 2D numerical simulation and the 4H-SiC DMOSFET structure results in a threshold voltage ($V_{TH}$) below $^{\sim}$3.8 V, and high figure of merit ($V_B\;^2/R_{SP,ON}$>$^{\sim}$200 $MW/cm^2$) for a power MOSFET in $V_B\;^{\sim}$800 V range.

A Study on the Bus of Platooning with C-V2X (C-V2X를 활용한 군집주행 버스에 대한 연구)

  • Back, Jae-hee;Shin, Yong-tae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2018.10a
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    • pp.325-328
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    • 2018
  • With the rapid development of autonomous driving technology, commercialization of freight cars and buses as well as passenger cars has come to the near future. As researches for commercialization of autonomous navigation are being actively carried out in various countries around the world, in accordance with the development of technology, this paper proposes a bus adopting a new concept of community driving technology based on C-V2X for more effective autonomous driving of buses do. In order to realize the cluster bus, we propose a more effective cluster bus using C-V2X, which is the core communication of the cluster driving, which is complementary to the existing V2X for inter-vehicle communication and vehicle-to-infrastructure communication.

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Low-Power CMOS On-Chip Voltage Reference Circuits (저전력 CMOS On-Chip 기준전압 발생회로)

  • Kwon, Duck-Ki;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of IKEEE
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    • v.4 no.2 s.7
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    • pp.181-191
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    • 2000
  • In this paper, two schemes of generating reference voltages using enhancement-mode MOS transistors and resistors are proposed. The first one is a voltage-mode scheme where the temperature compensation is made by summing a voltage component proportional to a threshold voltage and a voltage component proportional to a thermal voltage. In the second one, that is a current-mode scheme, the temperature compensation is made by summing a current component proportional to a threshold voltage and a current component proportional to a thermal voltage. The designed circuits have been simulated using a $0.65{\mu}m$ n-well CMOS process parameters. The voltage-mode circuit has a temperature coefficient less than $48.0ppm/^{\circ}C$ and a power-supply(VDD) coefficient less than 0.21%/V for a temperature range of $-30^{\circ}C{\sim}130^{\circ}C$ and a VDD range of $3V{\sim}12V$. The current-mode circuit has a temperature coefficient less than $38.2ppm/^{\circ}C$ and a VDD coefficient less than 0.8%/V for $-30^{\circ}C{\sim}130^{\circ}C\;and\; 4V{\sim}12V$. The power consumption of the voltage-mode and current-mode circuits are $27{\mu}W\;and\;65{\mu}W$ respectively for 5V and $30^{\circ}C$. Measurement results show that the voltage-mode reference circuit has a VDD coefficient less than 0.63%/V for $30^{\circ}C{\sim}100^{\circ}C$ and has a temperature coefficient less than $490ppm/^{\circ}C\;for\;3V{\sim}6V$. The proposed reference circuits are simple and thus easy to design. The proposed current-mode reference circuit can be designed to generate a wide range of reference voltages.

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A Distcussion on the Size Deviation Test of Raw Silk (生絲纖度檢査規定에 關한 考察)

  • Choi, Jin-Sub
    • Journal of Sericultural and Entomological Science
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    • v.25 no.1
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    • pp.44-50
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    • 1983
  • The study was carried out to suggest on opinion of the standardization of size deviation in the existing raw silk testing method. 1. The present grade A of size deviation stipulates 4.61 to 5.80 of standard deviation for 50 to 69 denier of mean value, however, the 5.80 standard deviation with the mean values of 50 and 69 denier belong to different distribution. 2. It is reasonable that the variation coefficients of grade 2A should be lower than that of grade A. However, the present testing method shows larger variation in grade 2A than in grade A. This is illustrated 9.00 for 69 denier in grade 2A and 8.41 for 70 denier in grade A. 3. The size deviation value compares the quality of raw silk with different mean value. Therefore, the standard deviation is recommended to be replaced by the C.V. value in determining the grade of silk. 4. The C.V. have a tendency to increase with lower grades below 6A for the size deviation below 33 denier with some inconsistencies. The figures should be adjusted so that the C.V. inconsistencies size deviation below 33 denier will be corrected. 5. The standard deviation increases with size under the same grade for the size deviations above 33 denier, however, the C.V. does not vary greatly with size deviation. 6. To rectify the above-mentioned inconsistencies the C.V. conversion and curvilinear regresion correction is recommended to improve the present silk testing method 7. The table of size deviation standard are as follows: Suggested standard of size deviation, unit: C.V. Value

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A Method of Interoperating Heterogeneous Simulation Middleware for L-V-C Combined Environment (L-V-C 통합 환경 실현을 위한 이기종 시뮬레이션 미들웨어 연동 방안)

  • Cho, Kunryun;No, Giseop;Jung, Sihyun;Keerativoranan, Nopphon;Kim, Chongkwon
    • Journal of KIISE
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    • v.42 no.2
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    • pp.213-219
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    • 2015
  • Simulation is used these days to verify the hypothesis or the new technology. In particular, National Defense Modeling & Simulation (M&S) is used to predict wartime situation and conduct the military training. National Defense M&S can be divided into three parts, live simulation, virtual simulation, and constructive simulation. Live simulation is based on the real environment, which allows more realistic sumulation; however, it has decreased budget efficiency, but reduced depictions of reality. In contrast, virtual and constructive simulations which are based on the virtual environment, have increased budget efficiency, but reduced depictions of reality. Thus, if the three parts of the M&S are combined to make the L-V-C combined environment, the disadvantages of each simulation can be complemented to increases the quality of the simulation. In this paper, a method of interworking heterogeneous simulation middeware for L-V-C combined environment is proposed, and the test results of interworking between Data Distribution Service (DDS) and High Level Architecture (HLA) are shown.

The literatual study on incurable case of C.V.A (중풍(中風) 불치증(不治症)에 대한 문헌적(文獻的) 고찰(考察))

  • Park, Jung jun;Kim, Yong Jin;Seol, In Chan;Hwang, Chi Won
    • Journal of Haehwa Medicine
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    • v.9 no.2
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    • pp.269-276
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    • 2001
  • In the literatual study about incurable case of C.V.A, the result were as follow: 1. The expressions of incurable C.V.A are sa(死), bulchi(不治), bulgabokchi(不可復治), hyung(凶), samang(死亡), danbulgu(斷不救), etc. 2. The symptoms of incurable C.V.A are balgiktomal(髮直吐沫),oudusangchan(搖頭上竄),augugijo(魚口氣粗),mokjingjiksi,ansohusungyuegue(眼小喉聲如鋸)myunjukyejang(面赤加粧), hanchulyueju(汗出如珠), sooneuimosang(循衣摸床), sinhonbuloe(神昏不語) dumyunsujokjogabchunghuk(頭面手足靑黑), dongjiguntong(動止筋痛), tohyulhayul(吐血下血), daetodaesa(大吐大瀉), gugaeanhab(口開眼合), suchul(手撤), bihan, yunyoe(遺尿) etc. 3. The pulse of incurable C.V.A is classified with maekgeubidaesakja(脈急而大數者) and maekgindaegeunjil(脈緊大急疾). 4. The symptoms of incurable C.V.A are classified into five viscerals and classify the differences between special symtom of each visceral and proenosis.

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SIA-LVC : Scalable Interworking Architecture for Military L-V-C Training Systems Based on Data Centric Middleware (SIA-LVC: 데이터 중심 미들웨어 기반 확장성 있는 국방 L-V-C 훈련체계 연동 아키텍쳐)

  • Kim, Won-Tae;Park, Seung-Min
    • KIPS Transactions on Computer and Communication Systems
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    • v.5 no.11
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    • pp.393-402
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    • 2016
  • A Military L-V-C system consists of distributed complex systems integrating Live systems working on physical wall-clock time, Virtual systems ruled by virtually pseudo realtime events on a computer, and Constructive systems only depending on the causal relationship between the continuous events. Recently many needs for L-V-C training systems are increasing in order to achieve the maximum training effects with low costs. While theoretical/logical researches or only partially interworking technologies have been proposed, there are few perfect interworking architectures for totally interoperating L-V-C systems in world-wide. In this paper, we design and develop a novel interworking architecture based on data centric middleware for the consistent global time with the same states on the entire L-V-C data and events by means of integrating the heterogeneous distributed middleware standards of each L-V-C system. In addition, simulated L-V-C systems based on real systems will be used for the efficiency and performance of the developed interworking architecture.

Interoperable Middleware Gateway Based on HLA and DDS for L-V-C Simulation Training Systems (L-V-C 훈련체계 연동을 위한 HLA, DDS 기반의 연동 미들웨어 게이트웨이)

  • Jun, Hyung Kook;Eom, Young Ik
    • IEMEK Journal of Embedded Systems and Applications
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    • v.10 no.6
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    • pp.345-352
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    • 2015
  • Recently, by developing many training systems in battle field, the demand for interconnecting and internetworking between Live, Virtual, Constructive training systems has been increased to support efficient data distribution and system control. But, there are lots of problems for them to interwork, because the existing researches only support L-L, V-V, C-C Interoperability. Therefore, we propose L-V-C gateway to provide interoperable simulation environment based on HLA and DDS between them. First, we illustrate FOM Management that parses RPR-FOM XML file to acquire Data information to be shared between them, and generates common data structure and source code used for L-V-C Gateway. L-V-C Gateway created from FOM Management supports Data Conversion and Quality of Service between HLA and DDS. HLA Federate and DDS Domainparticipant in L-V-C Gateway play a role of logical communication channel and relay data from HLA Federation to DDS Domain and vice versa.