• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.699-708
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• 2006

Bus splitting technique reduces bus energy by placing modules with frequent communications closely and using necessary bus segments in communications. But, previous bus splitting techniques can not be used in MPSoC platform, because it uses cache coherency protocol and all processors should be able to see the bus transactions. In this paper, we propose a bus splitting technique for MPSoC platform to reduce bus energy. The proposed technique divides a bus into several bus segments, some for private memory and others for shared memory. So, it minimizes the bus energy consumed in private memory accesses without producing cache coherency problem. We also propose a task allocation technique considering cache coherency protocol. It allocates tasks into processors according to the numbers of bus transactions and cache coherence protocol, and reduces the bus energy consumption during shared memory references. The experimental results from simulations say the bus splitting technique reduces maximal 83% of the bus energy consumption by private memory accesses. Also they show the task allocation technique reduces maximal 30% of bus energy consumed in shared memory references. We can expect the bus splitting technique and the task allocation technique can be used in multiprocessor platforms to reduce bus energy without interference with cache coherency protocol.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.76-85
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• 2016

This paper presents a method of decision on where bus splitting is needed to reduce fault current level of power systems and to satisfy the fault current constraints. The method employs a modified fault current constrained optimal power flow (FCC-OPF) with X variables for the candidate locations of splitting and for decision making on whether to split or not, it adopts soft-discretization by augmenting inversed U-shaped penalty terms. Also, this paper discusses the procedure on the adequate selection of bus splitting locations based on the results of the modified FCC-OPF, to reduce the total number of the actions taken.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.324-332
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• 2005

In general, bus system consumes a very significant portion of power in a chip. Bus splitting can be used to reduce the energy dissipation and to reduce the Propagation delay on the bus by lowering the parasitic load of each bus segment. Data exchange probability distribution between a set of interconnected processing elements affects the average energy dissipation of the splitted bus architectures. In this research, we have developed tree-based bus splitting techniques and design methodologies, as an extension of horizontally aligned bus splitting. We have developed the methodology to select near-optimal bus architectures for low energy dissipation when data exchange probability distribution of a system is given. Experimental results show that the proposed techniques can reduce energy dissipation on the bus by up to 83$\%$.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.651-654
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• 2005

In this paper, we designed ECC(Elliptic Curve Cryptographic) Processor with Bus-splitting mothod for embedded SoC. ECC SIP is designed by VHDL RTL modeling, and implemented reusably through the procedure of logic synthesis, simulation and FPGA verification. To communicate with ARM9 core and SIP, we designed SIP bus functional model according to AMBA AHB specification. The design of ECC Processor for platform-based SoC is implemented using the design kit which is composed of many devices such as ARM9 RISC core, memory, UART, interrupt controller, FPGA and so on. We performed software design on the ARM9 core for SIP and peripherals control, memory address mapping and so on.

• Progress in Superconductivity and Cryogenics
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• v.7 no.2
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• pp.16-20
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• 2005

As power systems grow more complex and power demands increase, the fault current tends to gradually increase. In the near future, the fault current will exceed a circuit breaker rating for some substations, which is an especially important issue in the Seoul metropolitan area because of its highly meshed configuration. Currently, the Korean power system is regulated by changing the 154kV system configuration from a loop connection to a radial system, by splitting the bus where load balance can be achieved, and by upgrading the circuit breaker rating. A development project applying 154kV Superconducting Fault Current Limiter (SFCL) to 154kV transmission systems is proceeding with implementation slated for after 2010. In this paper, SFCL is applied to reduce the fault current in power systems according to two different application schemes and their technical impacts are evaluated. The results indicate that both application schemes can regulate the fault current under the rating of circuit breaker, however, applying SFCL to the bus-tie location is much more appropriate from an economic view point.

• KIEE International Transactions on Power Engineering
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• v.4A no.4
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• pp.221-226
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• 2004

As power systems grow more complex and power demands increase, the fault current tends to gradually increase. In the near future, the fault current will exceed a circuit breaker rating for some substations, which is an especially important issue in the Seoul metropolitan area because of its highly meshed configuration. Currently, the Korean power system is regulated by changing the 154kV system configuration from a loop connection to a radial system, by splitting the bus where load balance can be achieved, and by upgrading the circuit breaker rating. A development project applying a 154kV Superconducting Fault Current Limiter (SFCL) to 154kV transmission systems is proceeding with implementation slated for after 2010. In this paper, SFCL is applied to reduce the fault current in power systems according to two different application schemes and their technical and economic impacts are evaluated. The results indicate that both application schemes can regulate the fault current under the rating of circuit breaker, however, applying SFCL to the bus-tie location is much more appropriate from an economic view point.

• Progress in Superconductivity and Cryogenics
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• v.5 no.1
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• pp.103-106
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• 2003

The short circuit current problem is one of the operational problems that need to be solved by power system engineers in Korea. It is an important issue in the Seoul metropolitan area especially because of highly meshed configuration. Currently, it is regulated by changing 154 kV system configuration from loop connection to radial system, by splitting of the bus where load balance can be achieved, and by upgrading circuit breaker rating. A development project for 154 kV/2 KA SFCL application to 154 kV transmission system after 2010 is proceeding. In this paper, a feasibility study of superconducting fault current limiter (SFCL) is carried out in Seoul metropolitan area to find out the effects of its application and feasibility. This study shows that it can reduce fault current considerably, and as it can minimize the upgrading of circuit breaker rating, the economic potential of SFCL is evaluated positively.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.4
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• pp.297-302
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• 2015

Replacing a manual switch installed in a feeder for a distribution system with an automatic one increases the reliability of the electric power system. This is because the automatic switch can shorten the duration of a fault the customer experiences by splitting the faulty section faster than the manual one does. However, improving the reliability of the distribution system may increase investment costs. Here, the investment costs include automatic switch cost, replacement work cost and labor cost. For this reason, importance should be attached to the proper balance between the increase of the investment costs and the improvement of the reliability of the distribution system. This article analyzed reliability index and economics when manual switches installed in a feeder (RBTS Bus2 model) was replaced by automatic ones. In addition, it attempted to draw the optimum rate of automation of manual switches by automatic ones using the GRG optimization method, considering the current economic requirements.

• KIEE International Transactions on Power Engineering
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• v.3A no.1
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• pp.1-6
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• 2003

As power systems grow more complex and power demands increase, the fault current tends to gradually increase. In the near future, the fault current will exceed a circuit breaker rating for some substations, which is an especially important issue in the Seoul metropolitan area because of its highly meshed configuration. Currently, the Korean power system is regulated by changing the 154 ㎸ system configuration from a loop connection to a radial system, by splitting the bus where load balance can be achieved, and by upgrading the circuit breaker rating. A development project applying 154 ㎸ Superconducting Fault Current Limiter(SFCL) to 154 ㎸ transmission systems is proceeding with implementation slated for after 2010. In this paper, the resistive and inductive SFCLs are applied to re-duce the fault current in Korean power system and their technical and economic impacts are evaluated. The results show that the application of SFCL can eliminate the need to upgrade the circuit breaker rat-ing and the economic potential of SFCL is evaluated positively.

• Proceedings of the KIEE Conference
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• summer
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• pp.421-423
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• 2004

As power system grows more complex and power demands increase, the fault current tends to gradually increase. In the near future, the fault current will exceed a circuit breaker rating for some substations, which is an especially important issue in the Seoul metropolitan area because of its highly meshed configuration. Currently, the Korean power system is regulated by changing the 154kV system configuration from a loop connection to a radial system, by splitting the bus where load balance can be achieved, and by upgrading the circuit breaker rating. A development project applying 154kV Superconducting Fault Current Limiter(SFCL) to 154kV transmission systems is proceeding with implementation slated for after 2010. In this paper, the expected price of SFCL in order to assure the economic feasibility is evaluated comparing with upgrading cost of ciui.1 breakers. The results show that the SFCL should be developed under seven times of price of circuit breaker to be competitive against upgrading circuit breakers.