• Title/Summary/Keyword: Bus operation

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Design and Operation Characteristics of 2.4MJ Pulse Power System for Electrothermal-Chemical(ETC) Propulsion(I) (전열화학추진용 2.4MJ 펄스파워전원의 설계와 동작특성(I))

  • Jin, Y.S.;Lee, H.S.;Kim, J.S.;Cho, J.H.;Lim, G.H.;Kim, J.S.;Chu, J.H.;Jung, J.W.;Hwang, D.W.
    • Proceedings of the KIEE Conference
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    • 2000.07c
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    • pp.1868-1870
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    • 2000
  • As a drive for an ETC (Electro-thermal Chemical) launcher, a large pulse power system of a 2.4MJ energy storage was designed, constructed and tested. The overall power system consists of eight capacitive 300kJ energy storage banks. In this paper we describe the design features, setup and operation test result of the 300kJ pulsed power module. Each capacitor bank of the 300kJ module consists of six 22kV 50kJ capacitors. A triggered vacuum switch (TVS-43) was adopted as the main pulse switch. Crowbar diode circuits, variable multi-tap inductors and energy dumping systems are connected to each high power capacitor bank via bus-bars and coaxial cables. A parallel crowbar diode stack is fabricated in coaxial structure with two series 13.5kV, 60kA avalanche diodes. The main design parameters of the 300kJ module are a maximum current of 180kA and a pulse width of 0.5 - 3ms. The electrical performances of each component and current output variations into resistive loads have been investigated.

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Efficient Interface circuits of Embedded Memory for RISC-based DSP Microprocessor (RICS-based DSP의 효율적인 임베디드 메모리 인터페이스)

  • Kim, You-Jin;Cho, Kyoung-Rok;Kim, Sung-Sik;Cheong, Eui-Seok
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.9
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    • pp.1-12
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    • 1999
  • In this paper, we designed an embedded processor with 128Kbytes EPROM and 4Kbytes SRAM based on GMS30C2132 which RISC processor with DSP functions. And a new architecture of bus sharing to control the embedded memory and external memory unit i proposed aiming at one-cycle access between memories and CPU. For embedded 128Kbytes EPROM, we designed the new expansion interface for data size at data ordering with memory organization and the efficient interface for test. The embedded SRAM supports an extended stack area high speed DSP operation, instruction cache and variable data-length control which is accessed with 4K modulo addressing schemes. The proposed new architecture and circuits reduced the memory access cycle time from 40ns and improved operation speed 2-times for program benchmark test. The chip is occupied $108.68mm^2$ using $0.6{\mu}m$ CMOS technology.

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Heater Design of a Cooling Unit for a Satellite Electro-Optical Payload using a Thermal Analysis (열해석을 이용한 위성 광학탑재체 냉각 장치의 히터설계)

  • Kim, Hui-Kyung;Chang, Su-Young;Choi, Seok-Weon
    • Aerospace Engineering and Technology
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    • v.10 no.2
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    • pp.20-28
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    • 2011
  • The electro-optical payload of a low-earth orbit satellite is thermally decoupled with the bus, which supports a payload for a mission operation. The payload has a cooling unit of FPA(Focal Plane Assembly) which has a thermal behavior increasing its temperature instantly during an operation in order to dissipate a waste heat into the space. The FPA cooling unit should include a radiator and heatpipes with a sufficient performance in worst hot condition, and a heater design to maintain its temperature above a minimum allowable temperature in the worst cold condition. In this paper, we analyzed the thermal requirements and the heater design constraints from the thermal analysis results for the current thermal design of the FPA cooling unit and the design elements of the better heater design were found.

On the Current Limiting Characteristics and Parameters of Superconducting Fault Current Limiter Introduced to 345kV Electric Power System due to Resistive-Type, Reactive-Type and Their Performance Comparison (유도형과 저항형 초전도한류기의 파라메타를 고려한 전력계통도입효과의 분석 및 성능평가에 관한 연구)

  • 홍원표;김용학
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.16 no.3
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    • pp.74-83
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    • 2002
  • The maximun short circuit current of modern power system is becoming so large that circuit breaker is not expected to be able to shut down the current in the future In order cut over-currents, a system composed of a superconducting fault current limiter(SFCL) and traditional breaker seems to provide a promising solution for furture power operation. In present paper, three line-to-ground fault is assumed to happen at the center of 345kV transmission lines in a large capacity electric power system. The superconducting fault current limiter was represented using a commutation type, which consists of a non-inductive superconducting coil and current limiting element (resistor or reactor). from the viewpoint of current limiting performance, the prevention of the voltage drop at the load bus and comparision characteristics for two type SFCL. Desired design specification and operation parameters of SECL were also given qualitatively by the performance.

CPLD Implementation of SEED Cryptographic Coprocessor (SEED 암호 보조 프로세서의 CPLD 구현)

  • Choi Byeong-Yoon;Kim Jin-Il
    • Journal of the Institute of Convergence Signal Processing
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    • v.1 no.2
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    • pp.177-185
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    • 2000
  • In this paper CPLD design of cryptographic coprocessor which implements SEED algorithm is described. To satisfy trade-off between area and speed, the coprocessor has structure in which 1 round operation is divided into three subrounds and then each subround is executed using one clock. To improve clock frequency, online precomputation scheme for round key is used. To apply the coprocessor to various applications, four operating modes such as ECB, CBC, CFB, and OFB are supported. The cryptographic coprocessor is designed using Altera EPF10K100GC503-3 CPLD device and its operation is verified by encryption or decryption of text files through ISA bus interface. It consists of about 29,300 gates and performance of CPLD chip is about 44 Mbps encryption or decryption rate under 18 Mhz clock frequency and ECB mode.

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The Digital Redundancy Design for Back-up Mode Operation of Aviation Intercom (항공용 인터콤의 백업 모드 운용을 위한 디지털 방식의 이중화 설계)

  • Jeong, Seong-jae;Cho, Kyung-hak;Kim, Dong-hyouk;Lee, Seong-woo
    • Journal of Advanced Navigation Technology
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    • v.26 no.5
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    • pp.358-364
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    • 2022
  • The Inter Communication System for avionics is in charge of processing all voice signals that internal calls between Pilot and Co-pilot, internal calls between Pilots and Crews, external calls through communication equipment such as Ultra/Very High Frequency Receiver/Transmitter(U/VHF RT), audio signal monitoring for navigation and mission equipment such as VHF Omnidirectional Range/Instrument Landing System(VOR/ILS), Tactical Air Navigation(TACAN), audio signal output for voice recording to Flight Data Recorder(FDR) and Data Transfer System(DTS), and warning/caution audio signal generate about the status and threat of aircraft. Because Inter Communication System for avionics is sensitive to noise in the case of analog audio signals, a redundant design that can protect audio signal from electromagnetic noise inside/outside of aircraft is required for the mission of pilots and crews. In this paper, Normal/Back-up operation mode and redundancy design plan based on digital method for the redundancy of the digital Inter Communication System for avionics and manufacturing, verification results are described.

Development of a Transmission/Distribution Integrated Analysis Hybrid Algorithm for System Operation Platform Including Distributed Generation (분산전원을 포함하는 시스템 운용 플랫폼을 위한 송배전 통합 해석 하이브리드 알고리즘 개발)

  • Song, Chong-Suk;Suh, Jae-Wan;Jang, Moon-Jong;Jang, Gil-Soo
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.27 no.1
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    • pp.35-45
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    • 2013
  • Owing to the increase in the penetration of distributed generation the DGs connected to the distribution system have an effect on the system conditions of the transmission system and neighboring distribution systems. This makes the separate analysis of the transmission and distribution system no longer valid and requires the consideration of both the system in the analysis process. This paper proposes a transmission/distribution integrated analysis hybrid algorithm that would ensure the accurate analysis of the system by reflecting the results of the transmission and distribution system analysis on each other. Different scenarios are being analysed in order to verify the effectiveness of the hybrid algorithm by observing the effects of the DG connected distribution system on the transmission system and neighboring distribution systems. The algorithm and simulations performed are being conducted by MATLAB and the IEEE 30 bus system and a test distribution system has been utilized for the transmission and distribution systems respectively.

Implementation and Validation of Earth Acquisition Algorithm for Communication, Ocean and Meteorological Satellite

  • Park, Sang-Wook;Lee, Young-Ran;Lee, Byoung-Sun;Hwang, Yoo-La;Lee, Un-Seob
    • Journal of Astronomy and Space Sciences
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    • v.28 no.4
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    • pp.345-354
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    • 2011
  • Earth acquisition is to solve when earth can be visible from satellite after Sun acquisition during launch and early operation period or on-station satellite anomaly. In this paper, the algorithm and test result of the Communication, Ocean and Meteorological Satellite (COMS) Earth acquisition are presented in case of on-station satellite anomaly status. The algorithms for the calculation of Earth-pointing attitude control parameters including those attitude direction vector, rotation matrix, and maneuver time and duration are based on COMS configuration (Eurostar 3000 bus). The coordinate system uses the reference initial frame. The constraint calculating available time-slot to perform the earth acquisition considers eclipse, angular separation, solar local time, and infra-red earth sensor blinding conditions. The results of Electronics and Telecommunications Research Institute (ETRI) are compared with that of the Astrium software to validate the implemented ETRI software.

Utilization of Energy Storage System based on the Assessment of Area of Severity in Islanded Microgrid

  • Lee, Kyebyung;Yoon, Minhan;Park, Chang-Hyun;Jang, Gilsoo
    • Journal of Electrical Engineering and Technology
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    • v.12 no.2
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    • pp.569-575
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    • 2017
  • This paper proposes a method to utilize an energy storage system (ESS) based on the assessment of an area of severity (AOS) to voltage sag. The AOS is defined as a set of the fault positions that can cause voltage sags at many buses simultaneously. The assessment of AOS helps to determine an optimal location of ESS installation to minimize the expected sag frequency (ESF) at concerned buses. The ESS has the ability not only to play traditionally known roles but also to mitigate voltage sag impact on renewable energy sources (RES) in the islanded microgrid. Accordingly, using the proposed method the ESS has additional features to prevent the operation failure of RESs and improve the stability of the microgrid. In order to verify the presented method, a case study was conducted on the sample microgrid system that is modified from an IEEE 57-bus system.

Security Cost Analysis with Linear Ramp Model using Contingency Constrained Optimal Power Flow

  • Lyu, Jae-kun;Kim, Mun-Kyeom;Park, Jong-Keun
    • Journal of Electrical Engineering and Technology
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    • v.4 no.3
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    • pp.353-359
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    • 2009
  • This paper proposes a novel technique for calculating the security costs that properly includes ramping constraints in the operation of a deregulated power system. The ramping process is modeled by a piecewise linear function with certain assumptions. During this process, a ramping cost is incurred if the permissible limits are exceeded. The optimal production costs of the power producers are calculated with the ramping cost included, considering a time horizon with N-1 contingency cases using contingency constrained optimal power flow (CCOPF), which is solved by the primal-dual interior point method (PDIPM). A contingency analysis is also performed taking into account the severity index of transmission line outages and its sensitivity analysis. The results from an illustrative case study based on the IEEE 30-bus system are analyzed. One attractive feature of the proposed approach is that an optimal solution is more realistic than the conventional approach because it satisfies physical constraints, such as the ramping constraint.