• ETRI Journal
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• 제28권3호
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• pp.397-400
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• 2006

The multi-layer advanced high-performance bus (ML-AHB) BusMatrix proposed by ARM is an excellent architecture for applying embedded systems with low power. However, there is one clock cycle delay for each master in the ML-AHB BusMatrix of the advanced microcontroller bus architecture (AMBA) design kit (ADK) whenever a master starts new transactions or changes the slave layers. In this letter, we propose an improved design method to remove the one clock cycle delay in the ML-AHB BusMatrix of an ADK. We also remarkably reduce the total area and power consumption of the ML-AHB BusMatrix of an ADK with the elimination of the heavy input stages.

• 대한전기학회논문지
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• 제32권12호
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• pp.435-440
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• 1983

The methods of forming the bus impedance matrix, which is mainly employed in fault analysis of power system, can be generally classified in catagories, (1) the one being the inverse matrix of bus admittance matrix, and (2) the other the bus impedance matrix succesive formation method by particular algorithms. The former method is theouetically elegant, but the formation and inverse of complex bus admittance matrix for large power system requires too much amounts of computer memory space and computing time. The latter method also requires too much memory space. Therefore, in this paper, an algorithm and computer program is introduced for the formation of a sparse bus impedance matrix which generates only the matching terms of the admittance matrix. So, this method can reduce the computer memory and computing time, and can be applied to fault analysis of large power system by small digital computer.

• 한국정보과학회논문지:시스템및이론
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• 제32권11_12호
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• pp.629-638
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• 2005

시스템 온 칩 설계에서 온 칩 버스는 전체 시스템의 성능을 결정하는 중요한 요소이다. 특히 프로세서, DSP 및 멀티미디어 IP와 같이 보다 높은 버스 대역폭을 요구하는 IP가 사용될 경우 온 칩 버스의 대역폭 문제는 더욱 심각해진다. 이에 따라 최근 ARM 사에서는 고성능 온 칩 버스 구조인 ML-AHB 버스 매트릭스를 제안하였다. ML-AHB 버스 매트릭스는 시스템 내의 다중 마스터와 다중 슬레이브간의 병렬적인 접근 경로를 제공하여 전체 버스 대역폭을 증가시켜주고, 최근 많은 프로세서 요소들을 사용하는 휴대형 기기 및 통신 기기 등에 적합한 고성능 온 칩 버스 구조이다. 하지만 내부 컴포넌트인 입력 스테이지와 무어 타입으로 구현된 중재 방식으로 인해 마스터가 새로운 전송을 수행할 때 또는 슬레이브 레이어를 변경할 때 마다 항상 1 클럭 사이클 지연 현상이 발생된다. 본 논문에서는 이러한 문제점을 해결하기 위해 기존 ML-AHB 버스 매트릭스 구조를 개선하였다. 기존 버스 매트릭스 구조에서 입력 스테이지를 제거하고, 개선된 구조에 적합하도록 중재 방식을 변경하여 1 클럭 사이클 지연 문제를 해결하였다. 개선된 결과 4-beat incrementing 버스트 타입으로 다수의 트랜잭션을 수행할 경우, 기존 ML-AHB 버스 매트릭스에 비해 전체 버스 트랜잭션 종료 시간 및 평균 지연 시간이 각각 약 $20\%,\;24\%$ 정도 짧아졌다. 또한 FPGA의 슬라이스 수는 기존의 ML-AHB 버스 매트릭스보다 약 $22\%$ 정도 감소하였고, 클럭 주기도 약 $29\%$ 정도 짧아졌다.

• 대한전기학회논문지:전력기술부문A
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• 제48권9호
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• pp.1081-1087
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• 1999

Load Flow calulation methods can usually be divided into Gauss-Seidel method, Newton-Raphson method and decoupled method. Load flow calculation is a basic on-line or off-line process for power system planning. operation, control and state analysis. These days Newton-Raphson method is mainly used since it shows remarkable convergence characteristics. It, however, needs considerable calculation time in construction and calculation of inverse Jacobian matrix. In addition to that, Newton-Raphson method tends to fail to converge when system loading is heavy and system has a large R/X ratio. In this paper, matrix equation is used to make algebraic expression and then to slove load flow equation and to modify above defects. And it preserve P-Q bus part of Jacobian matrix to shorten computing time. Application of mentioned algorithm to 14 bus, 39 bus, 118 bus systems led to identical results and the same numbers of iteration obtained by Newton-Raphson method. The effect of computing time reduction showed about 28% , 30% , at each case of 39 bus, 118 bus system.

• 대한전기학회논문지
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• 제41권5호
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• pp.459-467
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• 1992

This paper presents a new algorithm for the countermeasure to alleviate the line overloads due to contingency without shedding loads in a power system. This method for relieving the line overloads by line switching is based on obtaining the kine outage distribution factors-the linear sensitivity factors, which give the amount of change in the power flow of each line due to the removal of a line in a power system. There factors are made up of the elements of sparse bus reactance matrix and brach reactances. In this paper a fast algorithm and program is presented for obtaining only the required bus reactance elements which corresponds to a non-zero elements of bus admittance matrix, and elements of columns which correspond to two terminal buses of the overloaded(monitored) line. The proposed algorithm has been validated in tests on a 6-bus and the 30-bus test system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부A
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• pp.311-315
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• 1998

Load Flow calculation methods can usually be divided into Gauss-Seidel method, Newton-Raphson method and decoupled method. Load flow calculation is a basic on-line or off-line process for power system planning, operation, control and state analysis. These days Newton-Raphson method is mainly used since it shows remarkable convergence characteristics. It, however, needs considerable calculation time in construction and calculation of inverse Jacobian matrix. In addition to that, Newton-Raphson method tends to fail to converge when system loading is heavy and system has a large R/X ratio. In this paper, matrix equation is used to make algebraic expression and then to solve load flow equation and to modify above defects. And it preserve certain part of Jacobian matrix to shorten the time of calculation. Application of mentioned algorithm to 14 bus, 39 bus, 118 bus systems led to identical result and the number of iteration got by Newton-Raphson method. The effect of time reduction showed about 28%, 30%, at each case of 39 bus, 118 bus system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1989년도 하계종합학술대회 논문집
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• pp.216-220
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• 1989

Direct calculation algorithm for the elements of A matrix is suggested for a single machine connected to the infinite bus. Excitation system and power system stabilizer are included. When A matrix is partitioned into seven submatrices, we can identify the location of non-zero elements and formula for each element. No matrix inversion and multiplication are necessary.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 C
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• pp.918-922
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• 1998

With the development of industry, the qualitical advancement of power is needed. Since it is placed in the end step of power system, the fault at the distribution system causes some users blackout directly. So if the fault occurs, quick restoration is very important subject and, for the reason, induction of the distribution automation system is now being progressed briskly. For the quick restoration of the faulted distribution system, the load shedding of the blackout-area must be followed, and the other problems like the shedded load, faulted voltage and the rest may cause other accident. Accordingly load shedding must be based on the precise calculation technique during the distribution system load flow(dist flow) calculation. In these days because of its superior convergence characteristic the Newton-Raphson method is most widely used. The number of buses in the distribution system amounts to thousands, and if the fault occurs at the distribution system, the speed for the dist flow calculation is to be improved to apply to the On-Line system. However, Newton-Raphson method takes much time relatively because it must calculate the Jacobian matrix and inverse matrix at every iteration, and in the case of huge load, the equation is hard to converge. In this thesis. matrix equation is used to make algebraical expression and then to solve load flow equation and to modify above defects. Then the complex matrix is divided into real part and imaginary part to keep sparcity. As a result time needed for calculation diminished. Application of mentioned algorithm to 302 bus, 700 bus, 1004 bus system led to almost identical result got by Newton-Raphson method and showed constant convergence characteristic. The effect of time reduction showed 88.2%, 86.4%, 85.1% at each case of 302 bus, 700 bus system 86.4%, and 1004 bus system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 정기총회 및 추계학술대회 논문집 학회본부
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• pp.6-8
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• 1993

Short Circuit analysis is one of the most fundamental procedures for power system analysis problem. In order 10 solve the problem, In order to solve the problem, it's required to develop an advanced algorithm by which modified bus admittance matrix are easily computed for a large number of alternative network configuration. This paper proposes a new calculation method to efficiently modify the bus impedance matrix elements of large power system by method for removal of link, and presents its Practicality by applying the proposed method in the power system model.