• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.50-57
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• 2011

Conventional bus system architectures are composed of several components such as master, arbiter, decoder and slave modules. The arbiter plays a role in bus arbitration according to the selected arbitration method, since several masters cannot use the bus concurrently. Typical priority strategies used in high performance arbiters include static priority, round robin, TDMA and lottery. Typical arbitration algorithms always consider the bus priority primarily, while the bus utilization is always ignored. In this paper, we propose an arbitration method using bus utilization for the operating block of each master. We verify the performance compared with the other arbitration methods through the TLM(Transaction Level Model). Based on the performance verification, the conventional fixed priority and round-robin arbitration methods cannot set the bus utilization. Whereas, in the case of the conventional TDMA and lottery arbitration methods, more than 100,000 cycles of bus utilization can be set by the user, exhibiting differences of actual bus utilization up to 50% and 70%, respectively. On the other hand, we confirm that for the proposed arbitration method, the matched bus utilization set by the user was above 99% using approximately 1,000 cycles.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2078-2082
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• 2010

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. Conventional arbitration method is considered bus priority primarily, actual bus utilization didn't considered. In this paper, we propose arbitration method using bus utilization operating block of each master, we verify the performance compared with the other arbitration methods through throughput performance. From the result of performance verification, we confirm that proposed arbitration method, matched bus utilization set by the user 40%, 20%, 20%, 20%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.65-72
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• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.33-34
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• 2016

This paper presents a load sharing method based on the low bandwidth communication (LBC) applied to a DC microgrid in order to balance the state of charge (SOC) of the battery units connected in parallel to the common bus. In this method, SOC of each battery unit is transferred to each other through LBC to calculate average SOC value. After that, droop coefficients of battery units are adjusted according to the difference between SOC of each unit and average SOC value of all batteries in the system. The proposed method can effectively balance the SOC of battery units in charging and discharging duration with a simple low bandwidth communication system.

• Smart Media Journal
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• v.1 no.1
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• pp.27-35
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• 2012

In this paper, the performance analysis for multimedia video codec(MPEG-4, H.264) on on-chip network communication architecture is presented. The On-Chip Network (OCN) is the new communication architecture of multimedia SoC design that overcomes the limits of On-Chip Bus architecture by providing higher data traffic bandwidth, reusability and higher scalability. We compared the performance of MPEG-4, H.264 decoder based on-chip network and AMBA on-chip bus. Experimental results show that the performance of MPEG-4, H.264 based on on-chip network is improved over 33~56% compared to the design based on AMBA on-chip bus.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.207-215
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• 2004

In a hierarchical-bus multiprocessor system, cache coherence protocol has effect on system performance. Under a particular cache coherence protocol, system performance can be affected by bus bandwidth, memory size, and memory block size. Therefore sensitivity analysis is necessary for the part of multiprocessor system. In this paper, we set up cache coherence protocol for hierarchical-bus multiprocessor system, and compute probability of state of protocol, and analyze sensitivity for part of system by simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.310-317
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• 1993

This paper presents a mechanism for improving performance of the IEEE 802.6 MAN(Metropolitan Area Network), a dual-bus structured high-speed communication network, by a more efficient use of bandwidth. The MAN protocol is able to handle various traffic and offers better transmission speed than the conventional LAN, but the unidirectional bus structure and propagation delay of request bits results in unfairness since higher nodes use more bandwidth. As the number of stations and the distances between them are increased, the problem becomes mere serious. As a solution, this paper presents a method that every station enables to identify the used slots, and that a specified class denoted 'erasure station' has with the functions of destination release, slot reuse. As a result, it is export to improve network bandwidth values of each station and the throughput and delay time was analytically analyzed, and it is shown that according to computer simulation results, this mechanism improves the network performance.

• Journal of information and communication convergence engineering
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• v.14 no.3
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• pp.184-190
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• 2016

We present experimental demonstrations of electromagnetic bandgap (EBG) structures for the wideband suppression of radiated emissions from a power bus in high-speed printed circuit boards (PCBs). In most of the PCB designs, a parallel plate waveguide (PPW) structure is employed for a power bus. This structure significantly produces the wideband-radiated emissions resulting from parallel plate modes. To suppress the parallel plate modes in the wideband frequency range, the power buses based on the electromagnetic bandgap structure with a defected ground structure (DGS) are presented. DGSs are applied to a metal plane that is connected to a rectangular EBG patch by using a via structure. The use of the DGS increases the characteristic impedance value of a unit cell, thereby substantially improving the suppression bandwidth of the radiated emissions. It is experimentally demonstrated that the DGS-EBG structure significantly mitigates the radiated emissions over the frequency range of 0.5 GHz to 2 GHz as compared to the PPW.

• Journal of Information Processing Systems
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• v.7 no.4
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• pp.679-690
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• 2011

In this paper we consider a local area network (LAN) of dual mode service where one is a token bus and the other is a carrier sense multiple access with a collision detection (CSMA/CD) bus. The objective of the paper is to find the overall cell/packet dropping probability of a dual mode LAN for finite length queue M/G/1(m) traffic. Here, the offered traffic of the LAN is taken to be the equivalent carried traffic of a one-millisecond delay. The concept of a tabular solution for two-dimensional Poisson's traffic of circuit switching is adapted here to find the cell dropping probability of the dual mode packet service. Although the work is done for the traffic of similar bandwidth, it can be extended for the case of a dissimilar bandwidth of a circuit switched network.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.6
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• pp.760-772
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• 1999

The CAN is a serial communication protocol for distributed real-time control and automation systems. Data generated from field devices in the distributed control of power plant are classified into three categories: real-time event data, real-time control data, non-real-time data. These data share a CAN medium. If the traffic of the CAN protocol is not efficiently controlled, performance requirements of the power plant system could not be satisfied. This paper proposes a bandwidth allocation algorithm that can be applicable to the CAN protocol. The bandwidth allocation algorithm not only satisfies the performance requirements of the real-time systems in the power plant but also fully utilizes the bandwidth of CAN. The bandwidth allocation algorithm introduced in this paper is validated using the integrated discrete-event/continuous-time simulation model which comprises the CAN network and distributed control system of power plant.