• 융합정보논문지
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• 제11권11호
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• pp.159-165
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• 2021

본 삼차원 선택적 산화를 이용하여 20 nm 수준의 핀 폭과 점진적으로 증가된 소스/드레인 확장 영역을 갖는 핀 채널을 벌크 실리콘 기판에 제작하였다. 제안된 기법을 이용하여 삼차원 소자를 제작하기 위한 공정기법 및 단계를 상세히 설명하였다. 삼차원 소자 시뮬레이션을 통해, 제안된 소자의 주요 특징과 특성을 기존 FinFET 및 벌크 FinFET 소자와 비교하였다. 제안된 삼차원 선택적 산화 방식의 핀 채널 MOSFET는 기존의 소자들과 비교하여 더 큰 구동 전류, 더 높은 선형 트랜스컨덕턴스, 더 낮은 직렬 저항을 가지며, 거의 유사한 수준의 소형화 특성을 보이는 것을 확인하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1547-1552
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• 2003

In this paper, we present a planar single-crystalline silicon x-axis micro-gyroscope fabricated with a perfectly aligned vertical actuation combs on one silicon wafer, using the extended SBM technology. The fabricated x-axis micro-gyroscope has the resolution of 0.1 deg/sec, the bandwidth of 100 Hz. These research results allow integrating 6 axes inertial measurement (3 accelerations and 3 angular rates) on the same silicon substrate using the same process for the first time.

• 전자통신동향분석
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• 제5권1호
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• pp.55-70
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• 1990

SIMOX SOI is known to be one of the most useful technologies for fabrications of new generation ULSI devices. This paper describes the current status of SIMOX SOI technology for ULSI applications. The SIMOX wafer is vertically composed of buried oxide layer and silicon epitaxial layer on top of the silicon substrate. The buried oxide layer is used for the vertical isolation of devices The oxide layer is formed by high energy ion implantation of high dose oxygen into the silicon wafer, followed by high temperature annealing. SIMOX-based CMOS fabrication is transparent to the conventional IC processing steps without well formation. Furthermore, thin film CMOX/SIMOX can overcome the technological limitations which encountered in submicron bulk-based CMOS devices, i.e., soft-error rate, subthreshold slope, threshold voltage roll-off, and hot electron degradation can be improved. SIMOX-based bipolar devices are expected to have high density which comparable to the CMOX circuits. Radiation hardness properties of SIMOX SOI extend its application fields to space and military devices, since military ICs should be operational in radiation-hardened and harsh environments. The cost of SIMOX wafer preparation is high at present, but it is expected to reduce as volume increases. Recent studies about SIMOX SOI technology have demonstrated that the performance of the SIMOX-based submicron devices is superior to the circuits using the bulk silicon.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권2호
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• pp.132-139
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• 2000

This paper reports a novel micromachining process based on UV-LIGA process and (110) silicon anisotropic etching for fabrication of a high-aspect-ratio comb actuator. The comb electrodes are fabricated by (110) SILICON comb structure considering the etch-rate-ratio between (110) and (111) planes and lateral etch rate of a beam-type structure. The fabricated structure was$ 400\mum \; thick\; and\; 18\mum$ wide comb electrodes separated by $7\mim$ so that the height-gap ratio was about 57. Also considering resonant frequency of the comb actuator and the frequency-matching between sensing and driving mode for gyroscope application, we designed the number, width, height and length of the spring structures. Electroplated gold springs on both sides of the seismic mass were $15\mum\; wide,\; 14\mum\; thick\; and \; 500\mum$ long. The fabricated comb actuator had resonant frequency ay 1430Hz, which was calculated to be 1441Hz. The proposed fabrication process can be applicable to the fabrication of a high-aspect-ratio comb actuator for a large displacement actuator and precision sensors. Moreover, this combined process enables to fabricate a more complex structure which cannot be fabricate only by surface or bulk micromachining.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.874-877
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• 2001

SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

• 진공이야기
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• 제3권1호
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• pp.16-21
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• 2016

FinFETs are able to be scaled down to 22 nm and beyond while suppressing effectively short channel effect, and have superior performance compared to 2-dimensional (2-D) MOSFETs. Bulk FinFETs are built on bulk Si wafers which have less defect density and lower cost than SOI(Silicon-On-Insulator) wafers. In contrast to SOI FinFETs, bulk FinFETs have no floating body effect and better heat transfer rate to the substrate while keeping nearly the same scalability. The bulk FinFET has been developed at 14 nm technology node, and applied in mass production of AP and CPU since 2015. In the development of the bulk FinFETs at 10 nm and beyond, self-heating effects (SHE) is becoming important. Accurate control of device geometry and threshold voltage between devices is also important. The random telegraph noise (RTN) would be problematic in scaled FinFET which has narrow fin width and small fin height.

• Carbon letters
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• 제16권3호
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• pp.135-146
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• 2015

Graphite can be classified into natural graphite from mines and artificial graphite. Due to its outstanding properties such as light weight, thermal resistance, electrical conductivity, thermal conductivity, chemical stability, and high-temperature strength, artificial graphite is used across various industries in powder form and bulk form. Artificial graphite of powder form is usually used as anode materials for secondary cells, while artificial graphite of bulk form is used in steelmaking electrode bars, nuclear reactor moderators, silicon ingots for semiconductors, and manufacturing equipment. This study defines artificial graphite as bulk graphite, and provides an overview of bulk graphite manufacturing, including isotropic and anisotropic materials, molding methods, and heat treatment.

• 대한전자공학회논문지
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• 제27권10호
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• pp.106-112
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• 1990

다공질 실리콘을 열산화할 때 산화의 온도 의존성과 IR흡수 스펙트럼을 조사하여 다공질 실리콘외 산화특성을 조사하였다. PSL(porous silicon layer)을 $700^{\circ}C$에서 1시간, $1100^{\circ}C$에서 1시간으로 2단계 습식산화시켜 bulk 실리콘의 열산화막과 같은 성질의 수십 ${\mu}m$두께의 OPSL(oxidized porous silicon layer)을 짧은 시간에 형성시킬 수 있으며, 식각율과 항복전계는 산화온도와 산화 분위기에 크게 의존하는 것으로 나타났다. 이때 PSL의 산화율은 약 390nm/s이고, 항복전계는 1.0MV/cm~2.0MV/cm의 분포를 갖는다. 웨이퍼 휨을 측정하여 고온 열산화시 발생하는 산화막의 stress를 조사하였다. $1000^{\circ}C$ 이상의 고온에서 건식산화할 경우 발생하는 stress는 ${10^2}dyne/{cm^2}~{10^10}dyne/{cm^2}$로 측정되었다.

• 한국재료학회지
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• 제14권1호
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• pp.9-12
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• 2004

Metallic impurities, such as Fe, Cu, and Au, become generation and recombination centers for minority carriers when combined with oxide precipitates or silicon self-interstitial clusters. As these centers may cause leakage and discharge in silicon devices, their prevention through gettering of the metallic impurities is an important issue. In this article, key aspects of intrinsic gettering, such as oxygen control, wafer cleaning, device area denudation, and bulk oxygen precipitation are discussed, and a practical method of implementing intrinsic gettering is outlined.

• 한국광학회:학술대회논문집
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• 한국광학회 2003년도 제14회 정기총회 및 03년 동계학술발표회
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• pp.322-323
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• 2003

Silicon substrate was fabricated by bulk silicon micromachining and it's structure is based on a proof mass suspended by two beam. To monitor the acceleration, dynamic excitation of accelerometer was performed using a shaker. The attached FFPI and suspension beam are bent because support beam move with variation of the proof mass. Thus phase difference detected by the acceleration change. So we can know that resonance frequency of fabricated accelerometer is about 557 Hz and dynamic range was measured from 0 g to 2 g.