• Agribusiness and Information Management
• /
• v.1 no.2
• /
• pp.43-60
• /
• 2009

To improve the performance of wide-issue superscalar processors, it is essential to increase the width of instruction fetch and the issue rate. Removal of control hazard has been put forward as a significant new source of instruction-level parallelism for superscalar processors and the conditional branch prediction is an important technique for improving processor performance. Branch mispredictions, however, waste a large number of cycles, inhibit out-of-order execution, and waste electric power on mis-speculated instructions. Hence, the branch predictor with higher accuracy is necessary for good processor performance. In global-history-based predictors like gshare and GAg, many mispredictions come from commit update of the branch history. Some works on this subject have discussed the need for speculative update of the history and recovery mechanisms for branch mispredictions. In this paper, we present a new mechanism for recovering the branch history after a misprediction. The proposed mechanism adds an age_counter to the original predictor and doubles the size of the branch history register. The age_counter counts the number of outstanding branches and uses it to recover the branch history register. Simulation results on the SimpleScalar 3.0/PISA tool set and the SPECINT95 benchmarks show that gshare and GAg with the proposed recovery mechanism improved the average prediction accuracy by 2.14% and 9.21%, respectively and the average IPC by 8.75% and 18.08%, respectively over the original predictor.

• Journal of KIISE:Computer Systems and Theory
• /
• v.26 no.9
• /
• pp.1158-1165
• /
• 1999

조건부 분기 명령어(conditional branch instruction)의 잘못된 분기 예측(branch misprediction)은 프로세서의 성능 향상에 심각한 장애 요인이 되고 있다. 특히 시분할(time-sharing) 시스템과 같이 문맥 교환(context switch)이 발생하는 멀티프로그래밍 환경(multiprogramming environment)에서는 더욱 낮은 분기 예측 정확성(branch prediction accuracy)을 보인다. 본 논문에서는 문맥 교환이 발생하는 멀티프로그래밍 환경에서 높은 분기 예측 정확성을 보이는 중첩 분기 예측표 교환(Overlapped Predictor Table Switch, OPTS) 기법을 소개한다. 분기 예측표(predictor table)를 분할하여 각각의 프로세스(process)에 할당하는 OPTS 기법은 문맥 교환의 영향을 최소화함으로써 높은 분기 예측 정확성을 유지하는 분기 예측 방법이다.Abstract There is wide agreement that one of the most important impediments to the performance of current and future pipelined superscalar processors is the presence of conditional branches in the instruction stream. Accurate branch prediction is required to overcome this performance limitation. Many branch predictors have been proposed to help to alleviate this problem, including the two-level adaptive branch predictor, and more recently, hybrid branch predictor. In a less idealized environment, such as a time-sharing system, code of interest involves context switches. Context switches, even at fairly large intervals, can seriously degrade the performance of many of the most accurate branch prediction schemes. In this study, we measure the effect of context switch on the branch prediction accuracy in various situation and show the feasibility of our new mechanism, OPTS(Overlapped Predictor Table Switch), which save and restore branch history table at every context switch.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.1083-1086
• /
• 2005

Modern superscalar processors exploit Instruction Level Parallelism to achieve high performance by speculative techniques such as branch prediction. The indirect branch target prediction is very difficult compared to the prediction of direct branch target and branch direction, since it has dynamically polymorphic target. We present a accurate and hardware-efficient indirect branch target predictor. It can reduce the tags which has to be stored in the Indirect Branch Target Cache without a sacrifice of the prediction accuracy. We implement the proposed scheme on SimpleScalar and show the efficiency running SPEC95 benchmarks.

• Journal of the Korea Society for Simulation
• /
• v.8 no.3
• /
• pp.17-28
• /
• 1999

Recently studies have shown that conditional branches can be accurately predicted by recording the path leading up to the branch. But path predictors are more complex and uncompatible with existing pattern branch predictors. In order to solve these problems, we propose a simple path branch predictor(SPBP) that hashes together two most recent branch instruction addresses. In addition, we propose a pattern/path hybrid branch predictor composed of the SPBP and existing pattern branch predictors. Through the trace-driven simulation of six benchmark programs, the performance improvement by the proposed pattern/path hybrid branch prediction is analysed and validated. The proposed predictor can improve the prediction accuracy from 94.21% to 95.03%.

• The KIPS Transactions:PartA
• /
• v.15A no.4
• /
• pp.217-226
• /
• 2008

Branch prediction accuracy is critical for system performance in modern microprocessor architectures. The use of speculative update branch history provides substantial accuracy improvement in branch prediction. However, speculative update branch history is the information about uncommitted branch instruction and thus it may hurts program correctness, in case of miss-speculative execution. Therefore, speculative update branch history requires suitable recovery mechanisms to provide program correctness as well as performance improvement. In this paper, we propose recovery logics for speculative update branch history. The proposed solutions are recovery logics for both global history and local history. In simulation results, our solution provides performance improvement up to 5.64%. In addition, it guarantees the program correctness and almost 90% of additional hardware overhead is reduced, compared to previous works.

• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.5
• /
• pp.366-370
• /
• 2015

This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special instruction to extend an immediate value. We adopt a G-share branch predictor and eliminate the existing shortcomings. We verified the new branch predictor on a field-programmable gate array with the Dhrystone benchmark. The newly proposed EISC branch predictor also accomplishes higher branch prediction accuracy than a conventional branch predictor.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.58 no.7
• /
• pp.1443-1449
• /
• 2009

This paper presents a profiling model of a wide-window superscalar microprocessor using multiple branch prediction. The key idea is to apply statistical profiling technique to the superscalar microprocessor with a wide instruction window and a multiple branch predictor. The statistical profiling data are used to obtain a synthetical instruction trace, and the consecutive multiple branch prediction rates are utilized for running trace-driven simulation on the synthesized instruction trace. We describe our design and evaluate it with the SPEC 2000 integer benchmarks. Our performance model can achieve accuracy of 8.5 % on the average.

• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.6
• /
• pp.306-313
• /
• 2005

Conditional branch prediction is an important technique for improving processor performance. Branch mispredictions, however, waste a large number of cycles, inhibit out-of-order execution, and waste electric power on mis-speculated instructions. Hence, the branch predictor with higher accuracy is necessary for good processor performance. In global-history-based predictors like gshare and GAg, many mispredictions come from commit update of the history. Some works on this subject have discussed the need for speculative update of the history and recovery mechanisms for branch mispredictions. In this paper, we present a simple mechanism for recovering the branch history after a misprediction. The proposed mechanism adds an age_counter to the original predictor and doubles the size of the branch history register. The age_counter counts the number of outstanding branches and uses it to recover the branch history register. Simulation results on the Simplescalar 3.0/PISA tool set and the SPECINTgS benchmarks show that gshare and GAg with the proposed recovery mechanism improved the average prediction accuracy by 2.14$\%$ and 9.21$\%$, respectively and the average IPC by 8.75$\%$ and 18.08$\%$, respectively over the original predictor.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.803-804
• /
• 2006

This paper presents a multiple branch predictor with perceptrons. We describe our design and evaluate it with the SPEC 2000 benchmarks. Our predictor achieves increased accuracy than the previous multiple branch predictors.

• Journal of the Korean Association of Geographic Information Studies
• /
• v.17 no.4
• /
• pp.101-111
• /
• 2014

Spatial events are predictable using data mining classification algorithms. Decision trees have been used as one of representative classification algorithms. And they were normally used in the classification tasks that have label class values. However since using rule ranking methods, spatial prediction have been applied in the spatial prediction problems. This paper compared rule ranking methods for the spatial prediction application using a decision tree. For the comparison experiment, C4.5 decision tree algorithm, and rule ranking methods such as Laplace, M-estimate and m-branch were implemented. As a spatial prediction case study, landslide which is one of representative spatial event occurs in the natural environment was applied. Among the rule ranking methods, in the results of accuracy evaluation, m-branch showed the better accuracy than other methods. However in case of m-brach and M-estimate required additional time-consuming procedure for searching optimal parameter values. Thus according to the application areas, the methods can be selectively used. The spatial prediction using a decision tree can be used not only for spatial predictions, but also for causal analysis in the specific event occurrence location.