• The Journal of the Korea institute of electronic communication sciences
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• v.19 no.2
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• pp.409-416
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• 2024

With the expansion of floating-point operation requirements for fast high-speed data signal processing and logic operations, the speed of the floating-point operation unit is the key to affect system operation. This paper studies the performance characteristics of different floating-point multiplier schemes, completes partial product compression in the form of carry and sum, and then uses a carry look-ahead adder to obtain the result. Intel Quartus II CAD tool is used for describing Verilog HDL and evaluating performance results of the floating point multipliers. Floating point multipliers are analyzed and compared based on area, speed, and power consumption. The FMAX of modified Booth encoding with Wallace tree is 33.96 Mhz, which is 2.04 times faster than the booth encoding, 1.62 times faster than the modified booth encoding, 1.04 times faster than the booth encoding with wallace tree. Furthermore, compared to modified booth encoding, the area of modified booth encoding with wallace tree is reduced by 24.88%, and power consumption of that is reduced by 2.5%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.4
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• pp.548-555
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• 2022

This paper describes the hardware implementation of elliptic curve cryptography (ECC) used as a core operation in elliptic curve digital signature algorithm (ECDSA). The ECC processor supports eight operation modes (four point operations, four modular operations) on the NIST P-521 curve. In order to minimize computation complexity required for point scalar multiplication (PSM), the radix-4 Booth encoding scheme and modified Jacobian coordinate system were adopted, which was based on the complexity analysis for five PSM algorithms and four different coordinate systems. Modular multiplication was implemented using a modified 3-Way Toom-Cook multiplication and a modified fast reduction algorithm. The ECC processor was implemented on xczu7ev FPGA device to verify hardware operation. Hardware resources of 101,921 LUTs, 18,357 flip-flops and 101 DSP blocks were used, and it was evaluated that about 370 PSM operations per second were achieved at a maximum operation clock frequency of 45 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11A
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• pp.1092-1097
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• 2005

In this paper, we propose a low-power Booth multiplication which reduces the switching activities of partial products during multiplication process. Radix-4 Booth algorithm has a characteristic that produces the Booth encoded products with zero when input data have sequentially equal values (0 or 1). Therefore, partial products have higher chances of being zero when an input with a smaller effective dynamic range of two multiplication inputs is used as a multiplier data instead of a multiplicand. The proposed multiplier divides a multiplication expression into several multiplication expressions with smaller bits than those of an original input data, and each multiplication is computed independently for the Booth encoding. Finally, the results of each multiplication are added. This means that the proposed multiplier has a higher chance to have zero encoded products so that we can implement a low power multiplier with the smaller switching activity. Implementation results show the proposed multiplier can save maximally about $20\%$ power dissipation than a previous Booth multiplier.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12C
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• pp.1256-1261
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• 2005

In this paper, we propose a low-power Booth multiplication which reduces the switching activities of partial products during multiplication process. Radix-4 Booth algorithm has a characteristic that produces the Booth encoded products with zero when input data have sequentially equal values (0 or 1). Therefore, partial products have higher chances of being zero when an input with a smaller effective dynamic range of two multiplication inputs is used as a multiplier data instead of a multiplicand. The proposed multiplier divides a multiplication expression into several multiplication expressions with smaller bits than those of an original input data, and each multiplication is computed independently for the Booth encoding. Finally, the results of each multiplication are added. This means that the proposed multiplier has a higher chance to have zero encoded products so that we can implement a low power multiplier with the smaller switching activity. Implementation results show the proposed multiplier can save maximally about $20\%$ power dissipation than a previous Booth multiplier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.53-61
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• 2004

In this paper, we proposed a new architecture of MAC(Multiplier-Accumulator) to operate high-speed multiplication-accumulation. We used the MBA(Modified radix-4 Booth Algorithm) which is based on the 1's complement number system, and CSA(Carry Save Adder) for addition of the partial products. During the addition of the partial product, the signed numbers with the 1's complement type after Booth encoding are converted in the 2's complement signed number in the CSA tree. Since 2-bit CLA(Carry Look-ahead Adder) was used in adding the lower bits of the partial product, the input bit width of the final adder and whole delay of the critical path were reduced. The proposed MAC was applied into the DWT(Discrete Wavelet Transform) filtering operation for JPEG2000, and it showed the possibility for the practical application. Finally we identified the improved performance according to the comparison with the previous architecture in the aspect of hardware resource and delay.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.87-94
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• 2002

In this paper an asynchronous away multiplier with a parallel array structure is introduced. This parallel array structure is used to make the computation time faster with a lower Power consumption. Asymmetric parallel away structure is used to minimize the average computation time in an asynchronous multiplier. Simulation shows that this structure reduces the time needed for computation by 55% as compared to conventional booth encoding array structures and that the multiplier with the proposed away structure shows a reduction of 40% in the computational time with a relatively lower power consumption.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.3
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• pp.563-569
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• 2007

As the mobile communication and the semiconductor technology is improved continuously, mobile contents such as the multimedia service and the 2D/3D graphics which require high level graphics are serviced recently. Mobile chips should consume small die area and low power. In this paper, we design a truncated floating-point multiplier that is useful for the 2D/3D vector graphics in mobile devices. The truncated multiplier is based on the radix-4 Booth's encoding algorithm and a truncation algorithm is used to achieve small area and low power. The average percent error of the multiplier is as small as 0.00003% and neglectable for mobile applications. The synthesis result using 0.35um CMOS cell library shows that the number of gates for the truncated multiplier is only 33.8 percent of the conventional radix-4 Booth's multiplier.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.10
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• pp.27-35
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• 1997

In this paper, we propose a new scheme for the generation of partial products for VLSI fast parallel multiplier. It adopts a new encoding method which halves the number of partial products using 2x2 submultipliers and rearrangement of primitive partial products. The true 4-input CSA can be achieved with appropriate rearrangement of primitive partial products out of 2x2 submultipliers using the newly proposed theorem on binary number system. A 16bit x 16bit multiplier has been desinged using the proposed method and simulated to prove that the method has comparable speed and area compared to booth's encoding method. Much smaller and faster multiplier could be obtained with far optimization. The proposed scheme can be easily extended to multipliers with inputs of higher resolutions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.67-74
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• 2000

In this paper, a $54{\times}54$-bit multiplier based on a improved conditional sum adder is proposed. To reduce the multiplication time, high compression-rate compressors without Booth's Encoding, and a 108-bit conditional sum adder with separated carry generation block, are developed. Furthermore, a design technique based on pass-transistor logic is utilized for optimize the multiplication time and the power consumption by about 5% compared to that of conventional one. With $0.65{\mu}m$, single-poly, triple-metal CMOS process, its chip size is $6.60{\times}6.69\;mm^2$ and the multiplication time is 135.ns at a 3.3V power supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.307-310
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• 2001

A parameterized complex-number multiplier (PCMUL) core IP (Intellectual Property), which can be used as an essential arithmetic unit in baseband signal processing of digital communication systems, is described. The bit-width of the multiplier is parameterized in the range of 8-b~24-b and is user-selectable in 2-b step. The PCMUL_GEN, a core generator with GUI, generates VHDL code of a CMUL core for a specified bit-width. The IP is based on redundant binary (RB) arithmetic and a new radix4 Booth encoding/decoding scheme proposed in this paper. It results in a simplified internal structure, as well as high-speed, low-power, and area-efficient implementation. The designed IP was verified using Xilinx FPGA board.