• Journal of Electrical Engineering and Technology
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• 제10권3호
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• pp.1370-1376
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• 2015

Generally, an autotransformer(AT) feeding system consists of double tracks, up and down, with the trolley wire and feeder wire of the up and down tracks connected in the sectioning post(SP). Consequently, load current or fault current flows on two tracks based on catenary impedance characteristics, making it difficult to estimate catenary impedance accurately. This paper presents a technique for the estimation of catenary impedance using boosting current compensation based on the current division characteristics of an AT feeding system to improve the operation performance of impedance relay. To verify the technique, we model an AT feeding system through a power analysis program (PSCAD/EMTDC) and simulate various operation and fault conditions. Through the simulation, we confirmed that the proposed technique has estimated catenary impedance with a similar degree of accuracy to the actual catenary impedance

• 조명전기설비학회논문지
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• 제27권1호
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• pp.53-60
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• 2013

In this paper, a control algorithm for active power filter (APF), which compensates for the harmonics and power factor, boosting the DC-link voltage is proposed. The proposed scheme employs a pulse-width-modulation (PWM) voltage-source inverter. A simple algorithm to detect the load current harmonics is also proposed. The APF and charging circuit are implemented in one inverter system. Finally, the validity of the proposed scheme is investigated with simulated and experimental results for a prototype APF system rated at 3kVA.

• Journal of Electrical Engineering and Technology
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• 제10권1호
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• pp.195-204
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• 2015

In this paper, the development of a cost-effective active power filter/uninterruptible power supply (APF/UPS) system with seamless mode transfer is described. The proposed scheme employs a pulse-width-modulation (PWM) voltage-source inverter and has two operational modes. First, when the source voltage is normal, the system operates as an APF, which compensates for the harmonics and power factor while boosting the DC-link voltage to be ready for the disturbance, without an additional DC charging circuit. A simple algorithm to detect the load current harmonics is also proposed. Second, when the source voltage is out of the normal range (owing to sag, swell, or outage), it operates a UPS, which controls the output voltage constantly by discharging the DC-link capacitor. Furthermore, a seamless transfer method for the single-phase inverter between the APF mode and the UPS mode is also proposed, in which an IGBT switch with diodes is used as a static bypass switch. Dissimilar to a conventional SCR switch, the IGBT switch can implement a seamless mode transfer. During the UPS operation, when the source voltage returns to the normal range, the system operates as an APF. The proposed system has good transient and steady-state response characteristics. The APF, charging circuit, and UPS systems are implemented in one inverter system. Finally, the validity of the proposed scheme is investigated with simulated and experimental results for a prototype APF/UPS system rated at 3 kVA.

• 전자공학회논문지
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• 제50권7호
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• pp.122-130
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• 2013

본 논문에서는 주로 고속 디지털 통신시스템 응용을 위해 고해상도, 저전력 및 소면적을 동시에 만족하는 45nm CMOS 공정으로 제작된 4단 파이프라인 구조의 12비트 100MS/s ADC를 제안한다. 입력단 SHA 회로에는 높은 입력 주파수를 가진 신호가 인가되어도 12비트 이상의 정확도로 샘플링할 수 있도록 게이트-부트스트래핑 회로가 사용된다. 입력단 SHA 및 MDAC 증폭기는 요구되는 DC 이득 및 높은 신호스윙을 얻기 위해 이득-부스팅 구조의 2단 증폭기를 사용하며, 넓은 대역폭과 안정적인 신호정착을 위해 캐스코드 및 Miller 주파수 보상기법을 선택적으로 적용하였다. 채널길이 변조현상 및 전원전압 변화에 의한 전류 부정합을 최소화하기 위하여 캐스코드 전류 반복기를 사용하며, 소자의 부정합을 최소화하기 위하여 전류 반복기와 증폭기의 단위 넓이를 통일하여 소자를 레이아웃 하였다. 또한, 제안하는 ADC에는 전원전압 및 온도 변화에 덜 민감한 저전력 기준 전류 및 전압 발생기를 온-칩으로 집적하는 동시에 외부에서도 인가할 수 있도록 하여 다양한 시스템에 응용이 가능하도록 하였다. 제안하는 시제품 ADC는 45nm CMOS 공정으로 제작되었으며 측정된 DNL 및 INL은 각각 최대 0.88LSB, 1.46LSB의 값을 가지며, 동적성능은 100MS/s의 동작속도에서 각각 최대 61.0dB의 SNDR과 74.9dB의 SFDR을 보여준다. 시제품 ADC의 면적은 $0.43mm^2$ 이며 전력소모는 1.1V 전원전압 및 100MS/s 동작속도에서 29.8mW이다.