• 제목/요약/키워드: Boost wire

검색결과 3건 처리시간 0.014초

Coupled Inductor Design Method for 2-Phase Interleaved Boost Converters

  • Liang, Dong;Shin, Hwi-Beom
    • Journal of Power Electronics
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    • 제19권2호
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    • pp.344-352
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    • 2019
  • To achieve high efficiency and reliability, multiphase interleaved converters with coupled inductors have been widely applied. In this paper, a coupled inductor design method for 2-phase interleaved boost converters is presented. A new area product equation is derived to select the proper core size. The wire size, number of turns and air gap length are also determined by using the proposed coupled inductor design method. Finally, the validity of the proposed coupled inductor design method is confirmed by simulation and experimental results obtained from a design example.

A Novel Fault Location Scheme on Korean Electric Railway System Using the 9-Conductor Representation

  • Lee, Chang-Mu;Lee, Han-Sang;Yoon, Dong-Hee;Lee, Han-Min;Song, Ji-Young;Jang, Gil-Soo;Han, Byung-Moon
    • Journal of Electrical Engineering and Technology
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    • 제5권2호
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    • pp.220-227
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    • 2010
  • This paper presents a novel fault location scheme on Korean AC electric railway systems. On AC railway system, because of long distance, 40[km] or above, between two railway substations, a fault location technique is very important. Since the fault current flows through the catenary system, it must be modeled exactly to analyze the fault current magnitude and fault location. In this paper, suggesting the novel scheme of fault location, a 9-conductor modeling technique including boost wires and impedance bonds is introduced based on the characteristics of Korean AC electric railway. After obtaining a 9-conductor modeling, the railway system is constructed for computer simulation by using PSCAD/EMTDC. By case studies, we can verify superiority of a new fault location scheme and propose a powerful model for fault analysis on electric railway systems.

고효율 전류모드 승압형 DC-DC 컨버터용 집적회로의 설계 (A Design of Integrated Circuit for High Efficiency current mode boost DC-DC converter)

  • 이준성
    • 전자공학회논문지 IE
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    • 제47권2호
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    • pp.13-20
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    • 2010
  • 본 논문에서는 PWM을 활용한 전류모드 고효율 PWM DC-DC 전원변환 집적회로(Integrated Circuit)를 설계하였다. IC에 인가할 수 있는 최대 전압은 40[V]이며 입력 전압이 DC 2.8[V]~330[V]일 때 출력 전압을 이 보다 높은 전압으로 바꿀 수 있는 한편 외부 저항비나 트랜스의 권선비를 조정하여 원하는 DC 전압을 만들어 낼 수 있다. 출력전압의 3[%] 오차를 유지하면서 3[A] 이상의 전류를 부하에 공급할 수 있도록 구현하였다. 제작공정은 0.6[um], 2P_2M CMOS 공정을 사용하였다. 전원전압이 3.6[V]일 때 대기상태에서 소비전력은 1[mW]이하이고 최대 전력변환 효율은 약 86[%]이다. 칩 사이즈는 2100*2000[um2]이며, 칩을 소형패키지에 내장하여 조립하였기 때문에 휴대형기기나 소형 전자기기에 적용이 편리하게 되어 있다.