• Journal of Power Electronics
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• v.19 no.2
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• pp.344-352
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• 2019

To achieve high efficiency and reliability, multiphase interleaved converters with coupled inductors have been widely applied. In this paper, a coupled inductor design method for 2-phase interleaved boost converters is presented. A new area product equation is derived to select the proper core size. The wire size, number of turns and air gap length are also determined by using the proposed coupled inductor design method. Finally, the validity of the proposed coupled inductor design method is confirmed by simulation and experimental results obtained from a design example.

• Journal of Electrical Engineering and Technology
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• v.5 no.2
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• pp.220-227
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• 2010

This paper presents a novel fault location scheme on Korean AC electric railway systems. On AC railway system, because of long distance, 40[km] or above, between two railway substations, a fault location technique is very important. Since the fault current flows through the catenary system, it must be modeled exactly to analyze the fault current magnitude and fault location. In this paper, suggesting the novel scheme of fault location, a 9-conductor modeling technique including boost wires and impedance bonds is introduced based on the characteristics of Korean AC electric railway. After obtaining a 9-conductor modeling, the railway system is constructed for computer simulation by using PSCAD/EMTDC. By case studies, we can verify superiority of a new fault location scheme and propose a powerful model for fault analysis on electric railway systems.

• 전자공학회논문지 IE
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• v.47 no.2
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• pp.13-20
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• 2010

This paper describes a current mode PWM DC-DC converter IC for battery charger and supply power converter for portable electronic devices. The maximum supply voltage of IC is 40[V] and 2.8[V]~330[V] DC input power is converted to higher or programmed DC voltage according to external resistor ratio or wire winding ratio of transformer. The maximum supply output current is 3[A] over and voltage error of output node is within 3[%]. The whole circuit needed current mode PWM DC-DC converter circuit is designed. The package dimensions and number of external parts are minimized in order to get a smaller hardware size. The power consumption is smaller then 1[mW] at stand by period with supply voltage of 3.6[V] and maximum energy conversion efficiency is about 86[%]. This device has been designed in a 0.6[um] double poly, double metal 40[V] CMOS process and whole chip size is 2100*2000 [um2].