Reduction of the Number of Power States for High-level Power Models based on Clock Gating Enable Signals (클럭 게이팅 구동신호 기반 상위수준 전력모델의 전력 상태 수 감소)
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- Journal of the Institute of Electronics and Information Engineers
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- v.52 no.9
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- pp.28-35
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- 2015