• Title/Summary/Keyword: Board Level Package

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Board Level Reliability Evaluation for Package on Package

  • Hwang, Tae-Gyeong;Chung, Ji-Young
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2007.04a
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    • pp.37-47
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    • 2007
  • Factor : Structure Metal pad & SMO size Board level TC test : - Large SMO size better Board level Drop test : - Large SMO size better Factor : Structure Substrate thickness Board level TC test : - Thick substrate better Board level Drop test : - Substrate thickness is not a significant factor for drop test Factor : Material Solder alloy Board level TC test : - Not so big differences over Pb-free solder and NiAu, OSP finish Board level Drop test : - Ni/Au+SAC105, CuOSP+LF35 are better Factor : Material Pad finish Board level TC test : - NiAu/NiAu is best Board livel Drop test : - CuOSP is best Factor : Material Underfill Board level TC test - Several underfills (reworkable) are passed TCG x500 cycles Board level Drop test : - Underfill lots have better performance than non-underfill lots Factor : Process Multiple reflow Board level TC test : - Multiple reflow is not a significant actor for TC test Board level Drop test : N/A Factor : Process Peak temp Board level TC test : - Higher peak temperature is worse than STD Board level Drop test : N/A Factor : Process Stack method Board level TC test : - No big difference between pre-stack and SMT stack Board level Drop test : - Flux dipping is better than paste dipping but failure rate is more faster

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A Study on the/ Correlation Between Board Level Drop Test Experiment and Simulation

  • Kang, Tae-Min;Lee, Dae-Woong;Hwang, You-Kyung;Chung, Qwan-Ho;Yoo, Byun-Kwang
    • Journal of the Microelectronics and Packaging Society
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    • v.18 no.2
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    • pp.35-41
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    • 2011
  • Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

Effect of Underfill on $\mu$BGA Reliability ($\mu$BGA 장기신뢰성에 미치는 언더필영향)

  • 고영욱;신영의;김종민
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2002.05a
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    • pp.138-141
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    • 2002
  • There are continuous efforts in the electronics industry to a reduced electronic package size. Reducing the size of electronic packages can be achieved by a variety of means, and for ball grid array(BGA) packages an effective method is to decrease the pitch between the individual balls. Chip scale package(CSP) and BGA are now one of the major package types. However, a reduced package size has the negative effect of reducing board-level reliability. The reliability concern is for the different thermal expansion rates of the two-substrate materials and how that coefficient CTE mismatch creates added stress to the BGA solder joint when thermal cycled. The point of thermal fatigue in a solder joint is an important factor of BGA packages and knowing at how many thermal cycles can be ran before failure in the solder BGA joint is a must for designing a reliable BGA package. Reliability of the package was one of main issues and underfill was required to improve board-level reliability. By filling between die and substrate, the underfill could enhance the reliability of the device. The effect of underfill on various thermomechanical reliability issues in $\mu$BGA packages is studied in this paper.

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Thermo-Mechanical Interaction of Flip Chip Package Constituents (플립칩 패키지 구성 요소의 열-기계적 특성 평가)

  • 박주혁;정재동
    • Journal of the Korean Society for Precision Engineering
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    • v.20 no.10
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    • pp.183-190
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    • 2003
  • Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.

High-density Through-Hole Interconnection in a Silicon Substrate

  • Sadakata, Nobuyuki
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2003.09a
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    • pp.165-172
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    • 2003
  • Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

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Efficient Decoupling Capacitor Optimization for Subsystem Module Package

  • Lim, HoJeong;Fuentes, Ruben
    • Journal of the Microelectronics and Packaging Society
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    • v.29 no.1
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    • pp.1-6
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    • 2022
  • The mobile device industry demands much higher levels of integration and lower costs coupled with a growing awareness of the complete system's configuration. A subsystem module package is similar to a board-level circuit that integrates a system function in a package beyond a System-in-Package (SiP) design. It is an advanced IC packaging solution to enhance the PDN and achieve a smaller form factor. Unlike a system-level design with a decoupling capacitor, a subsystem module package system needs to redefine the role of the capacitor and its configuration for PDN performance. Specifically, the design of package's form factor should include careful consideration of optimal PDN performance and the number of components, which need to define the decoupling capacitor's value and the placement strategy for a low impedance profile with associated cost benefits. This paper will focus on both the static case that addresses the voltage (IR) drop and AC analysis in the frequency domain with three specific topics. First, it will highlight the role of simulation in the subsystem module design for the PDN. Second, it will compare the performance of double-sided component placement (DSCP) motherboards with the subsystem module package and then prove the advantage of the subsystem module package. Finally, it will introduce three-terminal decoupling capacitor (decap) configurations of capacitor size, count and value for the subsystem module package to determine the optimum performance and package density based on the cost-effective model.

BUMPLESS FLIP CHIP PACKAGE FOR COST/PERFORMANCE DRIVEN DEVICES

  • Lin, Charles W.C.;Chiang, Sam C.L.;Yang, T.K.Andrew
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2002.09a
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    • pp.219-225
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    • 2002
  • This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

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Deformation Behavior of MEMS Gyroscope Package Subjected to Temparature Change (온도변화에 따른 MEMS 자이로스코프 패키지의 변형측정)

  • Joo, Jin-Won;Choi, Yong-Seo;Choa, Sung-Hoon;Song, C.M.
    • Proceedings of the KSME Conference
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    • 2003.11a
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    • pp.1407-1412
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    • 2003
  • In MEMS devices, packaging induced stress or stress induced structure deformation become increasing concerns since it directly affects the performance of the device. In this paper, deformation behavior of MEMS gyroscope package subjected to temparature change is investigated using high-sensitivity $Moir{\acute{e}}$ interferometry. Using the real-time $Moir{\acute{e}}$ setup, fringe patterns are recorded and analyzed at several temperatures. Temperature dependent analyses of warpages and extensions/contractions of the package are presented. Linear elastic behavior is documented in the temperature region of room temperature to $125^{\circ}C$. Analysis of the package reveals that global bending occurs due to the mismatch of thermal expansion coefficient between the chip, the molding compond and the PCB.

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Design and Fabrication of the System in Package for the Digital Broadcasting Receiver (디지털 방송 수신용 System in Package 설계 및 제작)

  • Kim, Jee-Gyun;Lee, Heon-Yong
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.58 no.1
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    • pp.107-112
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    • 2009
  • This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.