• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.6
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• pp.719-725
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• 2019

We propose a 2.4-GHz CMOS power amplifier (PA) with a bypass structure to improve the power-added efficiency (PAE) in the low-power region. The primary winding of the output transformer is split into two parts. One of the primary windings is connected to the output of the power stage for high-power mode. The other primary winding is connected to the output of the driver stage for low-power mode. Operation of the high power mode is similar to conventional PAs. On the other hand, the output power of the driver stage becomes the output power of the overall PA in the low power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. We designed the CMOS PA using a 180-nm RFCMOS process. The measured maximum output power is 27.78 dBm with a PAE of 20.5%. At a measured output power of 16 dBm, the PAE is improved from 2.5% to 12.7%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.825-831
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• 2016

In this paper, a transimpedance amplifier based on a new DC offset cancellation (DCOC) method is proposed for WCDMA/LTE applications. The proposed method applies a sample and hold mechanism to the conventional DCOC method with a DC feedback loop. It prevents the removal of information around the DC, so it avoids signal-to-noise ratio degradation. It also reduces area and power consumption. It was designed in a $0.13{\mu}m$ deep n-well CMOS technology and drew a maximum current of 1.58 mA from a 1.2 V supply voltage. It showed a transimpedance gain of $80dB{\Omega}$, an input-referred noise current lower than 0.9 pA/${\surd}$Hz, an out-of-band input-referred 3rd-order intercept point more than 9.5 dBm, and an output DC offset lower than 10 mV. Its area is $0.46mm{\times}0.48mm$.

• ETRI Journal
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• v.42 no.6
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• pp.943-950
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• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.5
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• pp.513-520
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• 2003

In this paper, a novel design concept of frequency doubler using feedforward technique and DGS microstrip line is proposed. The feedforward loop plays a role of fundamental frequency suppression and DGS microstrip line suppresses over the 3rd order harmonic components. By using this new concept, the high suppression for the undesired signals could be achieved easily. The proposed technique is experimentally demonstrated in 1.87 GHz-to-3.74 GHz frequency doubler. The output power of -3 dBm at the frequency of 3.74 GHz(2f$\_$0/) is measured with 42.9 dB suppression of the fundamental frequency signal(f$\_$0/), 20.2 dB suppression of the 3rd harmonic signal(3f$\_$0/) and B9.7 dB suppression of the 4th harmonic signal(4f$\_$0/). The conversion loss of -2.34 dB ∼ -5.8 dB at the bandwidth of 100 MHz, the phase noise of -97.51 dB/Hz(＠10 kHz) were measured.

• Journal of the Optical Society of Korea
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• v.17 no.5
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• pp.357-361
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• 2013

A regenerative Er-doped fiber amplifier system for a high-repetition-rate optical pulse train is investigated for the first time. A signal pulse train with a wavelength tuning range of 18 nm is produced by a passive mode-locked fiber laser based on a nonlinear polarization rotation technique. In order to realize the amplification, an optical delay-line is used to achieve time match between the pulses' interval and the period of pulse running through the regenerative amplifier. The 16 dB gain is obtained for an input pulse train with a launching power of -30.4 dBm, a center wavelength of 1563.4 nm and a repetition rate of 15.3 MHz. The output properties of signal pulses with different center wavelengths are also discussed. The pulse amplification is found to be different from the regenerative amplification system for CW signals.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.20-25
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• 2007

The periodic domain-inversion in the selective areas of $Ti:LiNbO_3$ Mach-Zender waveguides was performed and band-pass modulators and single sideband (SSB) modulators were fabricated by using domain-reversal. The domain wall velocity was precisely controlled by real-time analysis of a poling-induced response current under an applied voltage. The domain wall velocity was significantly affected by the crystal orientation of the domain wall propagation which influenced the final domain geometry. In a certain case, the decomposition of $LiNbO_3$ crystal was observed, for example, under the condition of too fast domain wall propagation. The fabricated band-pass modulator with a periodic domain-inversion structure showed the maximum modulation efficiency at 30.3 GHz with 5.1 GHz 3dB-bandwidth, and SSB modulator was measured to show 33 dB USB suppression over LSB at 5.8 GHz RF.

• Journal of electromagnetic engineering and science
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• v.12 no.4
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• pp.234-239
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• 2012

This paper presents a compact K-band Doppler radar sensor for human vital signal detection that uses a radar configuration with only single coupler. The proposed radar front-end configuration can reduce the chip size and the additional RF power loss. The radar front-end IC is composed of a Lange coupler, VCO, and single balanced mixer. The oscillation frequency of the VCO is from 27.3 to 27.8 GHz. The phase noise of the VCO is -91.2 dBc/Hz at a 1 MHz offset frequency, and the output power is -4.8 dBm. The conversion gain of the mixer is about 11 dB. The chip size is $0.89{\times}1.47mm^2$. The compact Ka-band Doppler radar system was developed in order to demonstrate remote human vital signal detection. The radar system consists of a Ka-band Doppler radar module with a $2{\times}2$ patch array antenna, baseband signal conditioning block, DAQ system, and signal processing program. The front-end module size is $2.5{\times}2.5cm^2$. The proposed radar sensor can properly capture a human heartbeat and respiration rate at the distance of 50 cm.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.405-408
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• 2000

We designed and fabricated VCO using inductive reactance variation at 2GHz. A varactor diode is one of the main devices in VCO, which varies capacitance depending on reverse voltage. In this paper, a varactor diode is not used as a variable capacitive reactance device but as an inductive device. The circuit design and simulation have been carried out using HP-MDS. The fabricated VCO is measured using the HP 8532B spectrum analyzer and the HP 4352B VCO/PLL analyzer. The experimental result shows the phase noise -110dBc/Hz at a 100kHz offset frequency, the control voltage sensitivity of 23MHz/V and a -3.5dBm output power with a D.C. current consumption of 5.9mA. The simulation and measurements show exact agreement except with regard to the oscillation frequency. The measured oscillation frequency is lower than the simulation result because there is some parasitic inductance in the PCB layout.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.499-504
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• 2017

A UHF CMOS variable gain low-noise amplifier (LNA) is designed for mobile digital TV tuners. The proposed LNA adopts a feedback topology to cover a wide frequency range from 474 to 868 MHz, and it supports the notch filter function for the interoperability with the GSM terminal. In order to handle harmonic distortion by strong interferers, the gain of the proposed LNA is step-controlled while keeping almost the same input impedance. The proposed LNA is implemented in a $0.11{\mu}m$ CMOS process and consumes 6 mA at a 1.5 V supply voltage. In the measurement, it shows the power gain of greater than 16 dB, NF of less than 1.7 dB, and IIP3 of greater than -1.7 dBm for the UHF band.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.295-301
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• 2008

Recently, the demand on mm-wave (millimeter-wave) applications has increased dramatically. While circuits operating in the mm-wave frequency band have been traditionally implemented in III-V or SiGe technologies, recent advances in Si MOSFET operation speed enabled mm-wave circuits realized in a Si CMOS technology. In this work, a 58 GHz CMOS LC cross-coupled VCO (Voltage Controlled Oscillator) was fabricated in a $0.13-{\mu}m$ Si RF CMOS technology. In the course of the circuit design, active device models were modified for improved accuracy in the mm-wave range and EM (electromagnetic) simulation was heavily employed for passive device performance predicttion and interconnection parasitic extraction. The measured operating frequency ranged from 56.5 to 58.5 GHz with a tuning voltage swept from 0 to 2.3 V. The minimum phase noise of -96 dBc/Hz at 5 MHz offset was achieved. The output power varied around -20 dBm over the measured tuning range. The circuit drew current (including buffer current) of 10 mA from 1.5 V supply voltage. The FOM (Figure-Of-Merit) was estimated to be -165.5 dBc/Hz.