• Journal of the Korea Society of Computer and Information
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• v.24 no.8
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• pp.9-17
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• 2019

In this paper, we propose a block mapping technique applicable to NAND flash memory. In order to use the NAND flash memory with the operating system and the file system developed on the basis of the hard disk which is mainly used in the general PC field, it is necessary to use the system software known as the FTL (Flash Translation Layer). FTL overcomes the disadvantage of not being able to overwrite data by using the address mapping table and solves the additional features caused by the physical structure of NAND flash memory. In this paper, we propose a new mapping method based on the block mapping method for efficient use of the NAND flash memory. In the case of the proposed technique, the data modification operation is processed by using a blank page in the existing block without using an additional block for the data modification operation, thereby minimizing the block unit deletion operation in the merging operation. Also, the frequency of occurrence of the sequential write request and random write request Accordingly, by optimally adjusting the ratio of pages for recording data in a block and pages for recording data requested for modification, it is possible to optimize sequential writing and random writing by maximizing the utilization of pages in a block.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.2
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• pp.45-55
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• 1994

In this paper, a block based image approximation technique using the Self Affine System(SAS) from the fractal theory is suggested. Each block of an image is divided into 4 tiles and 4 affine mapping coefficients are found for each tile. To find the affine mapping cefficients that minimize the error between the affine transformed image block and the reconstructed image block, the matrix euation is solved by setting each partial differential coefficients to aero. And to ensure the convergence of coding block. 4 uniformly partitioned affine transformation is applied. Variable block size technique is employed in order to applynatural image reconstruction property of fractal image coding. Large blocks are used for encoding smooth backgrounds to yield high compression efficiency and texture and edge blocks are divided into smaller blocks to preserve the block detail. Affine mapping coefficinets are found for each block having 16$\times$16, 8$\times$8 or 4$\times$4 size. Each block is classified as shade, texture or edge. Average gray level is transmitted for shade bolcks, and coefficients are found for texture and edge blocks. Coefficients are quantized and only 16 bytes per block are transmitted. Using the proposed algorithm, the computational load increases linearly in proportion to image size. PSNR of 31.58dB is obtained as the result using 512$\times$512, 8 bits per pixel Lena image.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.1
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• pp.1-13
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• 2009

Flash memory is widely used as a storage medium of mobile devices such as MP3 players, cellular phones and digital cameras due to its tiny size, low power consumption and shock resistant characteristics. Currently, there are many studies to replace HDD with flash memory because of its numerous strong points. To use flash memory as a storage medium, FTL(Flash Translation Layer) is required since flash memory has erase-before-write constraints and sizes of read/write unit and erase unit are different from each other. Recently, new type of flash memory called "large block flash memory" is introduced. The large block flash memory has different physical structure and characteristics from previous flash memory. So existing FTLs are not efficiently operated on large block flash memory. In this paper, we propose an efficient FTL for large block flash memory based on FAST(Fully Associative Sector Translation) scheme and page-level mapping on data blocks.

• Journal of Advanced Navigation Technology
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• v.15 no.4
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• pp.616-625
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• 2011

There are two representative geometry rendering methods. One is Geometry Clipmaps, another is ROAM 2.0. We propose an extended Geometry Clipmaps algorithm which does not focus on CPU operation but the GPU for faster and wider visibility area. The extended algorithm presents mesh configuration method of each level by LOD, how to configurate Mesh network between levels, mesh block method for rendering optimization using VFC, and image mapping method to get high resolution up to 1 m.

• Journal of the Korean Society of Safety
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• v.36 no.2
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• pp.94-100
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• 2021

In general, the industrial complex is a place where factories of various industries are concentrated. It is only as efficient as it is designed. However, the risks vary as there are various industries. These features are also associated with various types of disasters. The dangers of natural disasters such as a typhoon, flood, and earthquake, as well as fire and explosions, are also latent. Many of these risks can make stable production and business activities difficult, resulting in massive direct and indirect damage. In particular, decades after its establishment, the vulnerabilities increase even more as aging and small businesses are considered. In this sense, it is significant to assess the vulnerability of the industrial complex. Thus analysing fire and explosion hazards as stage 1 of the vulnerability evaluation for the major potential disasters for the industrial complex. First, fire vulnerabilities were analyzed quantitatively. It is displayed in blocks for each company. The assessment block status and the fire vulnerability rating status were conducted by applying the five-step criteria. Level A is the highest potential risk step and E is the lowest step. Level A was 11.8% in 20 blocks, level B was 22.5% in 38 blocks, level C was 25.4% in 43 blocks, level D was 26.0% in 44 blocks, and level E was 14.2% in 24 blocks. Levels A and B with high fire vulnerabilities were analyzed at 34.3%. Secondly, the vulnerability for an explosion was quantitatively analyzed. Explosive vulnerabilities were analyzed at 4.7% for level A with 8 blocks, 3.0% for level B with 5, 1.8% for level C with 3, 4.7% for level D with 8, and 85.8% for level E with 145. Levels A and B, which are highly vulnerable to explosions, were 7.7 %. Thirdly, the overall vulnerability can be assessed by adding disaster vulnerabilities to make future assessments. Moreover, it can also assist in efficient safety and disaster management by visually mapping quantified data. This will also be used for the integrated control center of the N-Industrial Complex, which is currently being installed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.755-764
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• 1999

In this study, the system level network simulation is considered with adaptive array antenna in CDMA mobile communication system. A network simulation framework is implemented based on IS-95A/B system to consider dynamic handoff, system level network behavior, and deploying strategy into the overall CDMA mobile communication network under adaptive array algorithm. Its simulation model, such as vector channel model, adaptive beam forming antenna model, handoff model, and power control model, are described in detail with simulation block. In order to maximize SINR of received signal at antenna, maximin algorithm is particularly considered, and it is computed at each simulation snap shot with SINR based power control and handoff algorithm. Graphic user interface in this system level network simulator is also implemented to define the simulation environments and to represent simulation results on real mapping system. This paper also shows some features of simulation framework and simulation results.

• Journal of the Korea Society for Simulation
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• v.8 no.4
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• pp.33-51
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• 1999

In this study, the system level network simulation is considered with adaptive array antenna in CDMA mobile communication system. A network simulation framework is implemented based on IS-95A/B system to consider dynamic handoff, system level network behavior, and deploying strategy into the overall CDMA mobile communication network under adaptive array algorithm. Its simulation model, such as vector channel model, adaptive beam forming antenna model, handoff model, and power control model, are described in detail with simulation block. In order to maximize SINR of received signal at antenna, Maximin algorithm is particularly considered, and it is computed at each simulation snap shot with SINR based power control and handoff algorithm. Graphic user interface in this system level network simulator is also implemented to define the simulation environments and to represent simulation results on real mapping system. This paper also shows some features of simulation framework and simulation results.

• ETRI Journal
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• v.30 no.6
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• pp.790-798
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• 2008

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.10
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• pp.1167-1175
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• 2016

This paper proposes an efficient page-level mapping algorithm that reduces the erase count in the FTL for flash memory systems. By maintaining the weight for each write request in the request buffer, the proposed algorithm estimates the degree of temporal locality for each incoming write request. To exploit temporal locality deliberately for determination of hot request, the degree of temporal locality should be much higher than the reference point determined experimentally. While previous LRU algorithm treats a new write request to have high temporal locality, the proposed algorithm allows write requests that are estimated to have high temporal locality to access hot blocks to store hot data intensively. The pages are more frequently updated in hot blocks than warm blocks. A hot block that has most of invalid pages is always selected as victim block at Garbage Collection, which results in delayed erase operation and in reduced erase count. Experimental results show that erase count is reduced by 9.3% for real I/O workloads, when compared to the previous LRU algorithm.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.4
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• pp.71-81
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• 1999

We propose a new CPLD(Complexity Programmable Logic Device) technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG(Directed Acyclic Graph) type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB(Configurable Logic Block). In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time and the number of CLBs much more than the TEMPLA.