• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.586-589
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• 2003

Repeater is developed. Based on the systems The up-converter of the WCDMA Digital Optic pecifications, the structure of the up-converter is accomplished and its block diagram is drawn. The up-converter is implemented according to these block diagrams. Subsequently the low pass filter, the automatic level controlled attenuator, the frequency synthesizer and other components for the up-converter are designed and implemented, and a main board to integrate these modules is also manufactured. To reduce the noise floor of system and suppress the RF spurious noise, a PCB layout is performed carefully. For each module consisting of the up-converter and the entire system, the performance tests are accomplished to check the performance about the specifications.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.352-361
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• 2010

In this paper, a compact 20 W block-up-converter for C-band satellite communication is designed and implemented. The designed block up-converter consists of an intermediate frequency circuit, a mixer and local oscillator, a driver amplifier, a solid-state power amplifier, waveguide circuits, and a power supply module. To reduce the size of the block-up-converter, all circuits are assembled within an housing, so its dimension is just $21{\times}14{\times}11cm^3$. Especially, the waveguide filter and microstirp-to-waveguide transition are easily implemented using an housing. Also, to meet spurious and harmonics specification, various compact microstrip filters including an elliptic filter are integrated. Measurement results show that the developed block up-converter has good electrical performances: the output power of 43.7 dBm, the minimum gain of 65 dB, the gain flatness of ${\pm}1.84$, the IMD3 of -35 dBc, and the harmonic level of -105 dBc.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.247-250
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• 2012

This paper describes a DC-DC Boost converter for Thermoelectric Energy Harvesting. The designed converter boosts the $V_{DD}$ through a start-up block from a low output voltage of thermoelectric devices and the boosted $V_{DD}$ is used to operate the internal block circuits. When $V_{DD}$ reaches a predefined value, a detector circuit makes the start-up block turn off for minimizing current consumption. The final boosted $V_{OUT}$ is achieved by alternately operating the DC-DC converter for $V_{DD}$ and the other converter for final output $V_{OUT}$ according to the comparator output. Simulation results shows that the designed converter outputs 2.8V from an input voltage of 200mV. The area of the chip designed using a 0.35um CMOS process is $1.52mm{\times}0.95mm$ including pads.

• Journal of IKEEE
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• v.17 no.3
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• pp.284-293
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• 2013

This paper describes a DC-DC boost converter for thermoelectric energy harvesting. The designed converter boosts the VDD through a start-up block from a low-output voltage of a thermoelectric device and the boosted VDD is used to operate the internal control block. When the VDD reaches a predefined value, a detector circuit makes the start-up block turn off to minimize current consumption. The final boosted VOUT is achieved by alternately operating the DC-DC converter for VDD and the main DC-DC converter for VOUT according to the comparator outputs. Simulation results shows that the designed converter generates 2.65V from an input voltage of 200mV and its maximum power efficiency is 63%. The area of the chip designed using a 0.35um CMOS process is $1.3mm{\times}0.7mm$ including pads.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.91-95
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• 2008

This paper presents a direct-conversion I/Q up-mixer block, which supports $3{\sim}5$ GHz ultra-wideband(UWB) applications. It consists of a VI converter, a double-balanced mixer, a RF amplifier, and a differential-to-single signal converter. To achieve wideband characteristics over $3{\sim}5$ GHz frequency range, the double-balanced mixer adopts a shunt-peaking load. The proposed RF amplifier can suppress unwanted common-mode input signals with high linearity. The proposed direct-conversion I/Q up-mixer block is implemented using $0.18-{\mu}m$ CMOS technology. The measured results for three channels show a power gain of $-2{\sim}-9$ dB with a gain flatness of 1dB, a maximum output power level of $-7{\sim}-14.5$ dBm, and a output return loss of more than - 8.8 dB. The current consumption of the fabricated chip is 25.2 mA from a 1.8 V power supply.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.366-370
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• 2003

This paper introduces a new design and fabrication technology of 28 GHz low-cost up and down converter modules for digital microwave radios, The design of the converter module is based on unit circuit blocks, which are to be characterized using a special test fixture. Based on the cascade analysis of the module the 28 GHz up and down converter modules have been designed and implemented. The measured module performance agrees with the cascade analysis. New components such as a tapped edge-coupled filter and a new Ka-band waveguide-to-microstrip transition, which are less sensitive to fabrication tolerances, have been used in the module implementation.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.5
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• pp.115-123
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• 2000

In this paper, a block FIR(Finite Impulse Response) filtering architecture is proposed for IF digital down converter. Digital down converter consists of digital mixers. decimation filters and down samplers. In this proposed structure, it is shown that a efficient parallel decimation filter architecture can be produced by cancellation of inherent up sampling of the block filter and following down sampler Furthermore. it is shown that computational complexity of the proposed architecture is reduced by exploiting the block FIR structure and zero values of the digital mixers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1120-1128
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• 2004

In this paper, we has designed and implemented Up-converter for K-band with high IMD3 performance using balanced power amplifier. It is consisted of PA module and, Local Oscillator module with reject Filter, mixer module and If block, and Up-converter has a local loop path to decide whether it operate or not and has the sensing port to inspect output power level. According to the power budget of designed Up-converter, K-band balanced power amplifier was fabricated by commercial MMIC. Measurement results of up-converter show about 40dB Gain, PldB of 29dBm and OIP3 was 38.25dBm, that is good performance compared to power budgets. We has adjusted gate voltage of MMIC to control more than 30 dB gain. This up-converter was used in transceiver for PTP and PTMP, and applied to digital communication system that use QAM and QPSK modulation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.6
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• pp.715-720
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• 2016

This paper proposes a PWM (Pulse Width Modulation) voltage mode DC-DC step-up converter for portable devices. The converter, which is operated with a 1 MHz switching frequency, is capable of reducing the mounting area of passive devices, such as inductor and capacitor, and is suitable for compact mobile products. This step-up converter consists of a power stage and a control block. The circuit elements of the power stage are an inductor, output capacitor, MOS transistors Meanwhile, control block consist of OPAMP (operational amplifier), BGR (band gap reference), soft-start, hysteresis comparator, and non-overlap driver and some protection circuits (OVP, TSD, UVLO). The hysteresis comparator and non-overlapping drivers reduce the output ripple and the effects of noise to improve safety. The proposed step-up converter was designed and verified in Magnachip/Hynix 0.18um 1-poly, 6-metal CMOS process technology. The output voltage was 5 V with a 3.3 V input voltage, output current of 100 mA, output ripple less than 1% of the output voltage, and a switching frequency of 1 MHz. These designed DC-DC step-up converters could be applied to the Personal Digital Assistants(PDA), cellular Phones, Laptop Computer, etc.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.565-568
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• 2014

This paper presents a 0.2V DC/DC boost converter with regulated output for thermoelectric energy harvesting. To use low voltages from a thermoelectric device, a start-up circuit consisting of native NMOS transistors and resistors boosts an internal VDD, and the boosted VDD is used to operate the internal control block. When the VDD reaches a predefined value, a detector circuit makes the start-up block turn off to minimize current consumption. The final boosted VSTO is achieved by alternately operating the sub-boost converter for VDD and the main boost converter for VSTO according to the comparator outputs. When the VSTO reaches 2.4V, a buck converter starts to operate to generate a stabilized output VOUT. Simulation results shows that the designed converter generates a regulated 1.8V output from an input voltage of 0.2V, and its maximum power efficiency is 60%. The chip designed using a $0.35{\mu}m$ CMOS process occupies $1.1mm{\times}1.0mm$ including pads.