• 제목/요약/키워드: Block frequency

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음영 지역을 위한 다중 중계기 기반의 주파수 공간 블록 부호화 OFDMA 전송 시스템 (Space-Frequency Block Coded OFDMA Transmission System using Multiple Relays for Shadow Area)

  • 원희철
    • 한국산업정보학회논문지
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    • 제19권4호
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    • pp.1-8
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    • 2014
  • 음영 지역 해소 및 셀 커버리지 확대를 위하여 중계기를 활용하는 이동 통신 시스템이 널리 연구되고 있다. 본 논문에서는 중계기를 통해 다중 경로가 확보된 음영 지역에서 주파수 공간 블록 부호를 적용한 OFDMA(orthogonal frequency division multiple access) 전송 시스템을 제안한다. 다중 중계기에서 복원된 전송 신호에 대하여 주파수 공간 블록 부호를 적용하여 재전송함으로서 음영 지역 내 단말기의 수신 성능을 크게 향상시킬 수 있다. 실험을 통해, 제안된 주파수 공간 블록 부호화 OFDMA 전송 시스템의 성능이 기존의 단일 경로 OFDMA 전송 시스템의 성능보다 우수함을 확인한다.

High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey Algorithm and Its Folded Architecture

  • Park, Jeong-In;Lee, Ki-Hoon;Choi, Chang-Seok;Lee, Han-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제10권3호
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    • pp.193-202
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    • 2010
  • This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.

단일 반송파 전송 시스템을 위한 교번 스위칭 다중화 공간 주파수 블록 코딩 기법 (Alternate Time-Switched Multiplexed Space-Frequency Block Coding technique for Single-Carrier System)

  • 정혁구
    • 전기학회논문지P
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    • 제65권4호
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    • pp.316-320
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    • 2016
  • This paper proposes an alternate time-switched multiplexed space-frequency block coding technique for single-carrier modulation with frequency domain equalization. The traditional multiplexed space-frequency block coding technique for single-carrier modulation uses multiple groups of two transmitters and suppresses the interference signals of other SFBC groups at the receiver. In this paper, we reconfigure transmit signals to adapt them for alternate time-switched multiplexed SFBC for single-carrier modulation with frequency domain equalization and receiver structures and propose a structure for transmitter and receiver, show that its performance is better than the traditional algorithm by simulations.

Shuffled Discrete Sine Transform in Inter-Prediction Coding

  • Choi, Jun-woo;Kim, Nam-Uk;Lim, Sung-Chang;Kang, Jungwon;Kim, Hui Yong;Lee, Yung-Lyul
    • ETRI Journal
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    • 제39권5호
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    • pp.672-682
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    • 2017
  • Video compression exploits statistical, spatial, and temporal redundancy, as well as transform and quantization. In particular, the transform in a frequency domain plays a major role in energy compaction of spatial domain data into frequency domain data. The high efficient video coding standard uses the type-II discrete cosine transform (DCT-II) and type-VII discrete sine transform (DST-VII) to improve the coding efficiency of residual data. However, the DST-VII is applied only to the Intra $4{\times}4$ residual block because it yields relatively small gains in the larger block than in the $4{\times}4$ block. In this study, after rearranging the data of the residual block, we apply the DST-VII to the inter-residual block to achieve coding gain. The rearrangement of the residual block data is similar to the arrangement of the basis vector with a the lowest frequency component of the DST-VII. Experimental results show that the proposed method reduces the luma-chroma (Cb+Cr) BD rates by approximately 0.23% to 0.22%, 0.44% to 0.58%, and 0.46% to 0.65% for the random access, low delay B, and low delay P configurations, respectively.

Block Type 파일럿 배치를 적용한 OFDM 시스템의 등화 기법 개선 (Improved Equalization Technique of OFDM Systems Using Block Type Pilot Arrangement)

  • 김환우;김지헌
    • 한국음향학회지
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    • 제25권3호
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    • pp.113-120
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    • 2006
  • 본 논문은 slow 페이딩 채널에서 block type 파일럿 배치에 기반한 OFDM (Orthogonal Frequency Division Multiplexing) 시스템의 등화 기법을 다루고 있다. 수중 채널에서 얻을 수 있는 비트 속도는 셀룰러 폰이나 실내 무선 시스템과 같은 여타 통신 채널에 비해 상대적으로 낮은 편이며, 따라서 채널 추적시 도플러 효과가 중요한 파라미터가 된다. Coherent 복조 방식의 경우 도플러 주파수에 의한 잔여 평균위상에러는 시스템 성능에 치명적으로 작용할 수 있으며, 등화기만으로는 평균 도플러 쉬프트 효과에 대처하지 못할 수 있다. 공통 도플러 효과에 대처하기 위해 주파수 등화기와 더불어 위상에러 추적회로를 사용하여 회전 에러를 배제할 수 있다. 아울러 성능 저하를 최소화하는 수준에서 추적회로의 연산 부담을 줄일 수 있음을 시뮬레이션을 통해 증명하였다.

주변 블록의 움직임 벡터 빈도수에 기반한 움직임 벡터 교정을 적용한 프레임 율 변환 기법 (Frame Rate Up-Conversion Using the Motion Vector Correction based on Motion Vector Frequency of Neighboring blocks)

  • 이정훈;한동일
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2007년도 하계종합학술대회 논문집
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    • pp.259-260
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    • 2007
  • In this paper, a frame rate up-conversion algorithm using the motion vector frequency of neighboring blocks to reduce the block artifacts caused by failure of conventional motion estimation based on block matching algorithm is proposed. Experimental results show good performance of the proposed scheme with significant reduction of the erroneous motion vectors and block artifacts.

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Performance of SC-FDE System in UWB Communications with Imperfect Channel Estimation

  • Wang, Yue;Dong, Xiaodai
    • Journal of Communications and Networks
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    • 제9권4호
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    • pp.466-472
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    • 2007
  • Single carrier block transmission with frequency domain equalization(SC-FDE) has been shown to be a promising candidate in ultra-wideband(UWB) communications. In this paper, we analyze the performance of SC-FDE over UWB communications with channel estimation error. The probability density functions of the frequency domain minimum mean-squared error(MMSE) equalizer taps are derived in closed form. The error probabilities of single carrier block transmission with frequency domain MMSE equalization under imperfect channel estimation are presented and evaluated numerically. Compared with the simulation results, our semi-analytical analysis yields fairly accurate bit error rate performance, thus validating the use of the Gaussian approximation method in the performance analysis of the SC-FDE system with channel estimation error.

Block Error Performance Analysis of Mobile Multimedia Communication System in Nakagami fading Channel

  • 강희조;손성찬
    • 디지털콘텐츠학회 논문지
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    • 제5권2호
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    • pp.101-105
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    • 2004
  • The block error probabilities of noncoherent frequency shift keying in a Nakagami fading channel are presented in this papaer. The channel fading speed, show or fast. is consider in evaluating block error probabilities. The effectiveness of diversity combing and error correction coding in improving block error performance is examined. The effect of cochannel interference on block error performance is also studied in this paper.

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블록간 유사성과 선형조합을 이용한 블록화 현상 제거 알고리듬 (Blocking Artifact Reduction Algorithm Using Similarity between Blocks and Linear Combination)

  • 박경남;권기구;이건우;이석환;권성근;이건일
    • 한국통신학회논문지
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    • 제27권6A호
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    • pp.584-591
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    • 2002
  • 본 논문에서는 블록간의 유사성과 선형조합을 이용하여 블록화 현상 (blocking artifact)을 효율적으로 제거하는 알고리듬을 제안하였다. 제안한 방법에서는 모든 블록을 DCT 계수에 따라서 저주파 블록과 고주파 블록으로 나눈다. 그리고 블록화 현상이 나타나는 블록 경계면을 중심으로 하는 블록을 치역 블록 (range block)이라 정의하고, 이 치역 블록과 유사한 블록을 탐색영역 범위 안에서 찾은 다음 이를 정의역 블록 (domain block)이라라 정의한다. 그리고 탐색과정에서는 좀 더 정확한 정의역 블록을 참기 위해 치역 블록의 블록 경계면을 중심으로 양쪽으로 나누어진 부 블록 특성과 블록간 유사성을 이용하였다. 마지막으로 탐색과정에서찾은 정의역 블록과 블록화 현상이 발생한 치역 블록과의 선형 조합(linear combination)을 이용하여 치역 블록의 화소 값을 바꿈으로써 블록화 현상을 제거하였다. 모의 실험 결과로부터 제안한 방법이 기조의 방법에 비하여 PSNR 측면에서 0.04∼04 dB 정도의 향상을 얻었을 뿐만 아니라 주관적 화질 면에서도 우수한 성능을 나타냄을 확인하였다.

A Novel Fast Open-loop Phase Locking Scheme Based on Synchronous Reference Frame for Three-phase Non-ideal Power Grids

  • Xiong, Liansong;Zhuo, Fang;Wang, Feng;Liu, Xiaokang;Zhu, Minghua;Yi, Hao
    • Journal of Power Electronics
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    • 제16권4호
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    • pp.1513-1525
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    • 2016
  • Rapid and accurate phase synchronization is critical for the reliable control of grid-tied inverters. However, the commonly used software phase-locked loop methods do not always satisfy the need for high-speed and accurate phase synchronization under severe grid imbalance conditions. To address this problem, this study develops a novel open-loop phase locking scheme based on a synchronous reference frame. The proposed scheme is characterized by remarkable response speed, high accuracy, and easy implementation. It comprises three functional cascaded blocks: fast orthogonal signal generation block, fast fundamental-frequency positive sequence component construction block, and fast phase calculation block. The developed virtual orthogonal signal generation method in the first block, which is characterized by noise immunity and high accuracy, can effectively avoid approximation errors and noise amplification in a wide range of sampling frequencies. In the second block, which is the foundation for achieving fast phase synchronization within 3 ms, the fundamental-frequency positive sequence components of unsymmetrical grid voltages can be achieved with the developed orthogonal signal construction strategy and the symmetrical component method. The real-time grid phase can be consequently obtained in the third block, which is free from self-tuning closed-loop control and thus improves the dynamic performance of the proposed scheme. The proposed scheme is adaptive to severe unsymmetrical grid voltages with sudden changes in magnitude, phase, and/or frequency. Moreover, this scheme is able to eliminate phase errors induced by harmonics and random noise. The validity and utility of the proposed scheme are verified by the experimental results.