• The Journal of the Korea Contents Association
• /
• v.8 no.10
• /
• pp.37-44
• /
• 2008

This paper presented a solution to encryption and decryption problem suffering data transmission error for encrypted message transmission. Block cypher algorithms experience avalanche effect that a single bit error in an encrypted message brings substantial error bits after decryption. The proposed fault tolerant scheme addresses this error avalanche effect exploiting a multi-dimensional data array shuffling process and an error correction code. The shuffling process is to simplify the error correction. The shuffling disperses error bits to many data arrays so that each n-bit data block may comprises only one error bit. Thereby, the error correction scheme can easily restore the one bit error in an n-bit data block. This scheme can be extended on larger data blocks.

• ETRI Journal
• /
• v.33 no.6
• /
• pp.935-944
• /
• 2011

As a growing number of individuals are exposed to surveillance cameras, the need to prevent captured videos from being used inappropriately has increased. Privacy-related information can be protected through video encryption during transmission or storage, and several algorithms have been proposed for such purposes. However, the simple way of evaluating the security by counting the number of brute-force trials is not proper for measuring the security of video encryption algorithms, considering that attackers can devise specially crafted attacks for specific purposes by exploiting the characteristics of the target video codec. In this paper, we introduce a new attack for recovering contour information from encrypted H.264 video. The attack can thus be used to extract face outlines for the purpose of personal identification. We analyze the security of previous video encryption schemes against the proposed attack and show that the security of these schemes is lower than expected in terms of privacy protection. To enhance security, an advanced block shuffling method is proposed, an analysis of which shows that it is more secure than the previous method and can be an improvement against the proposed attack.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.8C
• /
• pp.767-774
• /
• 2007

A new transmit antenna selection and shuffling($AS^2$) method for spatially correlated double space time transmit diversity(DSTTD) systems is proposed. The proposed method allows dumb antennas and the superposition of multiple signals at the same transmit antenna, whereas the conventional methods consider the antenna shuffling(AS) only. According to the simulation result, the proposed method provides a 1.8 dB signal-to-noise ratio(SNR) gain over the conventional methods for spatially correlated transmit antennas. Although the number of candidates for $AS^2$ is much higher than that of AS, it is found that the number of candidates for $AS^2$ can be reduced to 36 by using the characteristics and properties of preprocessing matrices, and among them, only 6 candidates are almost always chosen. Next, we empirically compare the bit-error-rate (BER) performance of the proposed method with the conventional spatial multiplexing(SM) technique with antenna selection. Simulation results show that the proposed method outperforms the SM technique.

• Journal of Computing Science and Engineering
• /
• v.8 no.4
• /
• pp.187-198
• /
• 2014

In this paper an efficient image encryption scheme based on cyclic rotations and multiple blockwise diffusions with two chaotic maps is proposed. A Sin map is used to generate round keys for the encryption/decryption process. A Pomeau-Manneville map is used to generate chaotic values for permutation, pixel value rotation and diffusion operations. The encryption scheme is composed of three stages: permutation, pixel value rotation and diffusion. The permutation stage performs four operations on the image: row shuffling, column shuffling, cyclic rotation of all the rows and cyclic rotation of all the columns. This stage reduces the correlation significantly among neighboring pixels. The second stage performs circular rotation of pixel values twice by scanning the image horizontally and vertically. The amount of rotation is based on $M{\times}N$ chaotic values. The last stage performs the diffusion four times by scanning the image in four different ways: block of $8{\times}8$ pixels, block of $16{\times}16$ pixels, principal diagonally, and secondary diagonally. Each of the above four diffusions performs the diffusion in two directions (forwards and backwards) with two previously diffused pixels and two chaotic values. This stage makes the scheme resistant to differential attacks. The security and performance of the proposed method is analyzed systematically by using the key space, entropy, statistical, differential and performance analysis. The experimental results confirm that the proposed method is computationally efficient with high security.

• Journal of KIISE:Computing Practices and Letters
• /
• v.8 no.6
• /
• pp.736-745
• /
• 2002

In network delivery of compressed video, packets may be lost if the channel is unreliable like Internet. Such losses tend to of cur in burst like continuous bit-stream error. In this paper, we propose an effective error-concealment approach to which an error resilient video encoding approach is applied against burst errors and which reduces a complexity of error concealment at the decoder using data hiding. To improve the performance of error concealment, a temporal and spatial error resilient video encoding approach at encoder is developed to be robust against burst errors. For spatial area of error concealment, block shuffling scheme is introduced to isolate erroneous blocks caused by packet losses. For temporal area of error concealment, we embed parity bits in content data for motion vectors between intra frames or continuous inter frames and recovery loss packet with it at decoder after transmission While error concealment is performed on error blocks of video data at decoder, it is computationally costly to interpolate error video block using neighboring information. So, in this paper, a set of feature are extracted at the encoder and embedded imperceptibly into the original media. If some part of the media data is damaged during transmission, the embedded features can be extracted and used for recovery of lost data with bi-direction interpolation. The use of data hiding leads to reduced complexity at the decoder. Experimental results suggest that our approach can achieve a reasonable quality for packet loss up to 30% over a wide range of video materials.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.10 no.4
• /
• pp.1790-1806
• /
• 2016

Digital image encryption is widely used for image data security. JPEG standard compresses image with great performance on reducing file size. Thus, to encrypt an image in JPEG format we should keep the quality of original image and reduced size. This paper proposes a JPEG image encryption scheme based on quantized DC and non-zero AC coefficients inner category scrambling. Instead of coefficient value encryption, the address of coefficient is encrypted to get the address of cipher text. Then 8*8 blocks are shuffled. Chaotic iteration is employed to generate chaotic sequences for address scrambling and block shuffling. Analysis of simulation shows the proposed scheme is resistant to common attacks. Moreover, the proposed method keeps the file size of the encrypted image in an acceptable range compared with the plain text. To enlarge the cipher text possible space and improve the resistance to sophisticated attacks, several additional procedures are further developed. Contrast experiments verify these procedures can refine the proposed scheme and achieve significant improvements.

• The Journal of the Korea Contents Association
• /
• v.9 no.8
• /
• pp.91-98
• /
• 2009

This paper presents a solution to error avalanche of deciphering where radio noise brings random bit errors in encrypted image data under ubiquitous environment. The image capturing module is to be made comprising data compression and encryption features to reduce data traffic volume and to protect privacy. Block cipher algorithms may experience error avalanche: multiple pixel defects due to single bit error in an encrypted message. The new fault tolerant scheme addresses error avalanche effect exploiting a three-dimensional data shuffling process, which disperses error bits on many frames resulting in sparsely isolated errors. Averaging or majority voting with neighboring pixels can tolerate prominent pixel defects without increase in data volume due to error correction. This scheme has 33% lower data traffic load with respect to the conventional Hamming code based approach.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.9
• /
• pp.1115-1124
• /
• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.