• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.2
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• pp.91-100
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• 2011

The Triple Data Encryption Algorithm (Triple DES) is an international standard of block cipher, which composed of two encryption processes and one decryption process of DES to increase security level. In this paper, we proposed a Differential Fault Analysis (DFA) attack to retrieve secret keys using reduction of last round execution for each DES process in the Triple DES by fault injections. From the simulation result for the proposed attack method, we could extract three 56-bit secret keys using exhaustive search attack for $2^{24}$ candidate keys which are refined from about 9 faulty-correct cipher text pairs. Using laser fault injection experiment, we also verified that the proposed DFA attack could be applied to a pure microprocessor ATmega 128 chip in which the Triple DES algorithm was implemented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2333-2340
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• 2016

A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz.

• Journal of the Korea Society of Computer and Information
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• v.12 no.2 s.46
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• pp.63-70
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• 2007

The Data Encryption Standard (DES) is a block cipher that encrypts a 64 bit block of plaintext into a 64 bit block of ciphertext. The DES has been a worldwide standard for 20 years since it was adopted in 1976. strong. But, due to the rapid development of hardware techniques and cryptanalysis, the DES with 64-bit key is considered to be not secure at the present time. Therefore it became necessary to increase the security of DES. The NG-DES(New Generation DES)[1] is an encryption system which upgrades the encryption security of DES by the key extension and the usage of non-linear f function. It extends not only the size of plaintext and ciphertext to 128 bit but also the Fiestel structure used in each round. This structure has a weak point that the change of each bit of plaintext does not affect all bits of ciphertext simultaneously. In this paper, we propose a modified Fiestel structure of DES and thus increased confusion and diffusion by effectively cross-connecting between outputs in a round and inputs in next round.

• Journal of Korea Multimedia Society
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• v.21 no.8
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• pp.897-908
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• 2018

In this paper, we propose a security framework for a cluster drones network using the MAVLink (Micro Air Vehicle Link) application protocol based on FANET (Flying Ad-hoc Network), which is composed of ad-hoc networks with multiple drones for IoT services such as remote sensing or disaster monitoring. Here, the drones belonging to the cluster construct a FANET network acting as WTRP (Wireless Token Ring Protocol) MAC protocol. Under this network environment, we propose an efficient algorithm applying the Lightweight Encryption Algorithm (LEA) to the CTR (Counter) operation mode of WPA2 (WiFi Protected Access 2) to encrypt the transmitted data through the MAVLink application. And we study how to apply LEA based on CBC (Cipher Block Chaining) operation mode used in WPA2 for message security tag generation. In addition, a modified Diffie-Hellman key exchange method is approached to generate a new key used for encryption and security tag generation. The proposed method and similar methods are compared and analyzed in terms of efficiency.

• ETRI Journal
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• v.34 no.1
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• pp.76-86
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• 2012

The block cipher ARIA has been threatened by side-channel analysis, and much research on countermeasures of this attack has also been produced. However, studies on countermeasures of ARIA are focused on software implementation, and there are no reports about hardware designs and their performance evaluation. Therefore, this article presents an advanced masking algorithm which is strong against second-order differential power analysis (SODPA) and implements a secure ARIA hardware. As there is no comparable report, the proposed masking algorithm used in our hardware module is evaluated using a comparison result of software implementations. Furthermore, we implement the proposed algorithm in three types of hardware architectures and compare them. The smallest module is 10,740 gates in size and consumes an average of 47.47 ${\mu}W$ in power consumption. Finally, we make ASIC chips with the proposed design, and then perform security verification. As a result, the proposed module is small, energy efficient, and secure against SODPA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.498-501
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• 2002

In the process of Log-In to the system, clear User authentication is the beginning of the information protection service. In the open communication system of today, it is true that a password as security instrument and the inner mechanism of the system and cryptography algorithm for the support of this are also poor. For this reason, this dissertation had a final aim to design the user authentication system, which offer the accuracy and safety. It used RSA and CBC mode of DES as cryptography algorithm and used the Challenge-Response scheme at a authentication protocol and designed the User authentication system to which user access using one time password, output of token to guarantee the safety of the authentication protocol. Alto by using the Public key cryptography algorithm, it could embody the more safe User authentication system.

• Journal of Information Processing Systems
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• v.18 no.1
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• pp.59-74
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• 2022

During the last decade, the security of digital images has received considerable attention in various multimedia transmission schemes. However, many current cryptosystems tend to adopt a single-layer permutation or diffusion algorithm, resulting in inadequate security. A hierarchical bilateral diffusion architecture for color image encryption is proposed in response to this issue, based on a hyperchaotic system and DNA sequence operation. Primarily, two hyperchaotic systems are adopted and combined with cipher matrixes generation algorithm to overcome exhaustive attacks. Further, the proposed architecture involves designing pixelpermutation, pixel-diffusion, and DNA (deoxyribonucleic acid) based block-diffusion algorithm, considering system security and transmission efficiency. The pixel-permutation aims to reduce the correlation of adjacent pixels and provide excellent initial conditions for subsequent diffusion procedures, while the diffusion architecture confuses the image matrix in a bilateral direction with ultra-low power consumption. The proposed system achieves preferable number of pixel change rate (NPCR) and unified average changing intensity (UACI) of 99.61% and 33.46%, and a lower encryption time of 3.30 seconds, which performs better than some current image encryption algorithms. The simulated results and security analysis demonstrate that the proposed mechanism can resist various potential attacks with comparatively low computational time consumption.

• Journal of IKEEE
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• v.22 no.1
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• pp.38-45
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• 2018

An integrated cryptographic processor that efficiently integrates ARIA, AES block ciphers and Whirlpool hash function into a single hardware architecture is described. Based on the algorithm characteristics of ARIA, AES, and Whirlpool, we optimized the design so that the hardware resources of the substitution layer and the diffusion layer were shared. The round block was designed to operate in a time-division manner for the round transformation and the round key expansion of the Whirlpool hash, resulting in a lightweight hardware implementation. The hardware operation of the integrated ARIA-AES-Whirlpool crypto-processor was verified by Virtex5 FPGA implementation, and it occupied 68,531 gate equivalents (GEs) with a 0.18um CMOS cell library. When operating at 80 MHz clock frequency, it was estimated that the throughputs of ARIA, AES block ciphers, and Whirlpool hash were 602~787 Mbps, 682~930 Mbps, and 512 Mbps, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.485-487
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• 2017

The whirlpool hash function adopted as an ISO / IEC standard 10118-3 by the international standardization organization is an algorithm that provides message integrity based on an SPN (Substitution Permutation Network) structure similar to AES block cipher. In this paper, we describe the hardware implementation of the Whirlpool hash function. The round block is designed with a 64-bit data path and encryption is performed over 10 rounds. To minimize area, key expansion and encryption algorithms use the same hardware. The Whirlpool hash function was modeled using Verilog HDL, and simulation was performed with ModelSim to verify normal operation.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.402-413
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• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.