• Title/Summary/Keyword: Block Cipher AES

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MPW Implementation of Crypto-processor Supporting Block Cipher Algorithms of PRESENT/ARIA/AES (블록 암호 알고리즘 PRESENT/ARIA/AES를 지원하는 암호 프로세서의 MPW 구현)

  • Cho, Wook-lae;Kim, Ki-bbeum;Bae, Gi-chur;Shin, Kyung-wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.164-166
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    • 2016
  • PRESENT/ARIA/AES의 3가지 블록 암호 알고리즘을 지원하는 암호 프로세서를 MPW(Multi-Project Wafer)칩으로 구현하였다. 설계된 블록 암호 칩은 PRmo(PRESENT with mode of operation) 코어, AR_AS(ARIA_AES) 코어, AES-16b 코어로 구성된다. PRmo는 80/128-비트 마스터키와, ECB, CBC, OFB, CTR의 4가지 운영모드를 지원한다. 128/256-비트 마스터키를 사용하는 AR_AS 코어는 서로 내부 구조가 유사한 ARIA와 AES를 통합하여 설계하였다. AES-16b는 128-비트 마스터키를 지원하고, 16-비트 datapath를 채택하여 저면적으로 구현하였다. 설계된 암호 프로세서를 FPGA검증을 통하여 정상 동작함을 확인하였고, 0.18um 표준 셀 라이브러리로 논리 합성한 결과, 100 KHz에서 52,000 GE로 구현이 되었으며, 최대 92 MHz에서 동작이 가능하다. 합성된 다중 암호 프로세서는 MPW 칩으로 제작될 예정이다.

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A White Box Implementation of Lightweight Block Cipher PIPO (경량 블록 암호 PIPO의 화이트박스 구현 기법)

  • Ham, Eunji;Lee, Youngdo;Yoon, Kisoon
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.32 no.5
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    • pp.751-763
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    • 2022
  • With the recent increase in spending growth in the IoT sector worldwide, the importance of lightweight block ciphers to encrypt them is also increasing. The lightweight block cipher PIPO algorithm proposed in ICISC 2020 is an SPN-structured cipher using an unbalanced bridge structure. The white box attack model refers to a state in which an attacker may know the intermediate value of the encryption operation. As a technique to cope with this, Chow et al. proposed a white box implementation technique and applied it to DES and AES in 2002. In this paper, we propose a white box PIPO applying a white box implementation to a lightweight block cipher PIPO algorithm. In the white box PIPO, the size of the table decreased by about 5.8 times and the calculation time decreased by about 17 times compared to the white box AES proposed by Chow and others. In addition, white box PIPO was used for mobile security products, and experimental results for each test case according to the scope of application are presented.

A Study on a Method of Identifying a Block Cipher Algorithm to Increase Ransomware Detection Rate (랜섬웨어 탐지율을 높이기 위한 블록암호 알고리즘 식별 방법에 관한 연구)

  • Yoon, Se-won;Jun, Moon-seog
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.28 no.2
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    • pp.347-355
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    • 2018
  • Ransomware uses symmetric-key algorithm such as a block cipher to encrypt users' files illegally. If we find the traces of a block cipher algorithm in a certain program in advance, the ransomware will be detected in increased rate. The inclusion of a block cipher can consider the encryption function will be enabled potentially. This paper proposes a way to determine whether a particular program contains a block cipher. We have studied the implementation characteristics of various block ciphers, as well as the AES used by ransomware. Based on those characteristics, we are able to find what kind of block ciphers have been contained in a particular program. The methods proposed in this paper will be able to detect ransomware with high probability by complementing the previous detection methods.

A Cryptoprocessor for AES-128/192/256 Rijndael Block Cipher Algorithm (AES-128/192/256 Rijndael 블록암호 알고리듬용 암호 프로세서)

  • 안하기;박광호;신경욱
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.3
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    • pp.427-433
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    • 2002
  • This paper describes a design of cryptographic processor that implements the AES(Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation, the round block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.-V supply.

Design and Implementation of TFTP Protocol Supporting Network Security Functionalities (보안기능을 지원하는 TFTP 프로토콜의 설계 및 구현)

  • Yuen, Seoung-uk;Kwon, Hyun-kyung;Ok, Sung-Jin;Kang, Jung-Ha;Kim, Eun-Gi
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.653-656
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    • 2013
  • TFTP(Trivial File Transfer Protocol)는 UDP(User Datagram Protocol) 기반의 파일 전송 프로토콜이다. TFTP는 프로토콜 구조가 단순하여 작은 크기의 데이터를 빠른 속도로 전송할 때 사용된다. 하지만 TFTP는 보안 기능을 지원하지 않기 때문에 데이터 노출의 위험이 있다. 본 논문에서는 Diffie-Hellman 키 교환 방식과 AES-CBC(Advanced Encryption Standard-Cipher Block Chaining) 암호화 방식을 이용하여 TFTP 프로토콜에 보안 기능을 추가하였다. Diffie-Hellman 키 교환 방식을 이용하여 두 사용자 간에 비밀 키를 공유하도록 하였고, AES-CBC 암호화를 지원하여 기밀성을 제공하도록 하였다. 수신된 데이터는 암호화 과정의 역으로 복호화를 수행하였다. WireShark 프로그램을 통하여 암호화된 데이터가 전송 되는 것을 확인하였다.

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The Hardware Design and Implementation of a New Ultra Lightweight Block Cipher (새로운 초경량 블록 암호의 하드웨어 설계 및 구현)

  • Gookyi Dennis, A.N.;Park, Seungyong;Ryoo, Kwangki
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.10
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    • pp.103-108
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    • 2016
  • With the growing trend of pervasive computing, (the idea that technology is moving beyond personal computers to everyday devices) there is a growing demand for lightweight ciphers to safeguard data in a network that is always available. For all block cipher applications, the AES is the preferred choice. However, devices used in pervasive computing have extremely constraint environment and as such the AES will not be suitable. In this paper we design and implement a new lightweight compact block cipher that takes advantage of both S-P network and the Feistel structure. The cipher uses the S-box of PRESENT algorithm and a key dependent one stage omega permutation network is used as the cipher's P-box. The cipher is implemented on iNEXT-V6 board equipped with virtex-6 FPGA. The design synthesized to 196 slices at 337 MHz maximum clock frequency.

SPN Block cipher SSB having same structure in encryption and decryption (암호와 복호가 동일한 SPN 블록 암호 SSB)

  • Cho, Gyeong-Yeon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.4
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    • pp.860-868
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    • 2011
  • Feistel and SPN are the two main structures in a block cipher. Feistel is a symmetric structure which has the same structure in encryption and decryption, but SPN is not a symmetric structure. In this paper, we propose a SPN block cipher so called SSB which has a symmetric structure in encryption and decryption. The proposed SSB is composed of the even numbers of N rounds. Each round consists of a round key addition layer, a subsitution layer, a byte exchange layer and a diffusion layer. The subsitution layer of the odd round is inverse function of one of the even round. And the diffusion layer is a MDS involution matrix. The differential and linear attack probability of SSB is $2^{-306}$ which is same with AES. The proposed symmetric SPN block cipher SSB is believed to construct a safe and efficient cipher in Smart Card and RFID environments which is in limited hardware and software resources.

The Analysis of Cipher Padding Problem for Message Recovery Security Function of Honey Encryption (허니암호의 메시지 복구보안 기능을 위한 암호패딩 문제점 분석)

  • Ji, Changhwan;Yoon, Jiwon
    • Journal of KIISE
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    • v.44 no.6
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    • pp.637-642
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    • 2017
  • Honey Encryption (HE) is a technique to overcome the weakness of a brute-force attack of the existing password-based encryption (PBE). By outputting a plausible plaintext even if the wrong key is entered, it provides message recovery security which an attacker can tolerate even if the attacker tries a brute-force attack against a small entropy secret key. However, application of a cipher that requires encryption padding to the HE present a bigger problem than the conventional PBE method. In this paper, we apply a typical block cipher (AES-128) and a stream cipher (A5 / 1) to verify the problem of padding through the analysis of the sentence frequency and we propose a safe operation method of the HE.

Analysis of the Efficiency for Some Selected Double-Block-Length Hash Functions Based on AES/LEA (AES/LEA 기반 이중블록길이 해쉬함수에 대한 효율성 분석)

  • Kim, Dowon;Kim, Jongsung
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.26 no.6
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    • pp.1353-1360
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    • 2016
  • We analyze the efficiency of the double-block-length hash functions, Abreast-DM, HIROSE, MDC-2, MJH, MJH-Double based on AES or LEA. We use optimized open-source code for AES, and our implemented source code for LEA. As a result, the hash functions based on LEA are generally more efficient than those, based on AES. In terms of speed, the hash function with LEA are 6%~19% faster than those with AES except for Abreast-DM. In terms of memory, the hash functions with LEA has 20~30 times more efficient than those with AES.

A Lightweight Implementation of AES-128 Crypto-Core (AES-128 크립토 코어의 경량화 구현)

  • Bae, Gi-Chur;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.05a
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    • pp.171-173
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    • 2016
  • 128-비트의 마스터 키를 지원하는 블록암호 AES-128을 IoT 보안에 적합하도록 경량화하여 구현하였다. 키 스케줄러와 라운드 블록을 8 비트 데이터 패스로 구현하고, 다양한 최적화 방법을 적용함으로써 하드웨어를 최소화시켰으며, 100 MHz 클록 주파수에서 4,400 GE의 작은 게이트로 구현되었다. Verilog HDL로 설계된 AES 크립토 코어를 Vertex5 XC5VSX50T FPGA 디바이스에 구현하여 올바로 동작함을 확인하였다.

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