• Journal of the Korea Institute of Information Security & Cryptology
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• v.30 no.3
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• pp.349-356
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• 2020

GIFT is a PRESENT-like cryptographic algorithm proposed in CHES 2017 and used S-box that can be implemented through a bit-slice technique[1]. Since bit-permutation is used as a linear layer, it can be efficiently implemented in hardware, but bit-slice implementation in software requires a specific conversion process, which is costly. In this paper, we propose a new bit-permutation that enables efficient bit-slice implementation and GIFT-64-variant using it. GIFT-64-variant has better safety than the existing GIFT in terms of differential and linear cryptanalysis.

• 전기의세계
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• v.31 no.11
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• pp.775-786
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• 1982

Bit-slice 마이크로프로세서의 구조를 설명하고, bit-slice시스템의 설계를 위해 필요한 마이크로 인스트럭숀의 구성과 pipelining 기법에 관해 토의한다.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1449-1453
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• 1987

A microprogrammable Bit Slice Sinal Processor for image processing is implemented. Processing speed is increased by the parallelism in horizontal microprogram using 120bits microcode, pipelined architecture, 2 bank memory switching that interfaces with the Host through DMA, a variable clock control, overflow checking H/W,look-up table method and cache memory. With this processor, a DCT algorithm which uses 2-D FFT is performed. The execution time for $512{\times}512{\times}8$ image is 12 sec when 16 bit operation is runned, and the recovered image has acceptable quality with MSE 0.276%.

• The Journal of Information Technology
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• v.3 no.1
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• pp.61-72
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• 2000

In this paper, we propose a bit-sliced modular multiplication algorithm and a bit-sliced modular multiplier design meeting the increasing crypto-key size for RSA public key cryptosystem. The proposed bit-sliced modular multiplication algorithm was designed by modifying the Walter's algorithm. The bit-sliced modular multiplier is easy to expand to process large size operands, and can be immediately applied to RSA public key cryptosystem.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.4 no.2
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• pp.29-33
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• 1986

• The Science & Technology
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• v.11 no.9 s.112
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• pp.36-40
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• 1978

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.63-69
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• 1998

In this paper, we propose a new Bit-Rate control algorithm based on bit usage matching to substitute encoded GOP(s) for new GOP(s) in MPEG-2 bitstream. It iteratively encodes current picture according to quantization value of previous picture and records bit-usage of each slice until nearly target bits are used. With target bits falling in two output bits, quantization value of slice should be changed to alleviate output bit error. We use recorded bit-usage information to decide which slices should be encoded with one quantization value and others with another. As every macroblock has different activity, we change macroblock quantization value using slice quantization value and activity value. The simulation results demonstrate that the fluctuation of the output bits can be kept within few-several tens of bits while maintaining the quality of the reconstructed pictures at a relatively stable level.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.2
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• pp.171-179
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• 2011

Feistel and SPN are the two main structures in a block cipher. Feistel is a symmetric structure which has the same structure in encryption and decryption, but SPN is not a symmetric structure. Encrypt round function and decrypt round function in SPN structure have three parts, round key addition and substitution layer with S-box for confusion and permutation layer for defusion. Most SPN structure for example ARIA and AES uses 8 bit S-Box at substitution layer, which is vulnerable to Square attack, Boomerang attack, Impossible differentials cryptanalysis etc. In this paper, we propose a SPN which has a symmetric structure in encryption and decryption. The whole operations of proposed algorithm are composed of the even numbers of N rounds where the first half of them, 1 to N/2 round, applies a right function and the last half of them, (N+1)/2 to N round, employs an inverse function. And a symmetry layer is located in between the right function layer and the inverse function layer. The symmetric layer is composed with a multiple simple bit slice involution S-Boxes. The bit slice involution S-Box symmetric layer increases difficult to attack cipher by Square attack, Boomerang attack, Impossible differentials cryptanalysis etc. The proposed symmetric SPN block cipher with bit slice involution S-Box is believed to construct a safe and efficient cipher in Smart Card and RFID environments where electronic chips are built in.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1569-1572
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• 1987

The major objective of this paper is the design of control unit based on the bit slice technique. The branch control unit is device that provides 16-way branch when used in conjuction with the Microprogram Sequencer. The Next address control unit is designed specifically for next address control of the Microprogram Sequencer.

• Journal of Biomedical Engineering Research
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• v.6 no.2
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• pp.15-22
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.