• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.1141-1144
• /
• 2005

일반 컴퓨터에서 중앙처리장치와 메모리 사이의 병목 현상인 "Von Neumann Bottleneck"을 보이는데 본 논문에서는 이러한 문제점을 해소하고 검색위주의 응용분야에서 우수한 성능을 보이는 확장 가능한 범용 Associative Processor(AP) 구조를 제안하였다. 본 연구에서는 Associative computing을 효율적으로 수행할 수 있는 명령어 세트를 제안하였으며 다양하고 대용량 응용분야에도 적용할 수 있도록 구조를 확장 가능하게 설계함으로써 유연한 구조를 갖는다. 12 가지의 명령어가 정의되었으며 프로그램이 효율적으로 수행될 수 있도록 명령어 셋을 구성하고 연속된 명령어를 하나의 명령어로 구현함으로써 처리시간을 단축하였다. 제안된 프로세서는 bit-serial, word-parallel로 동작하며 대용량 병렬 SIMD 구조를 갖는 32 비트 범용 병렬 프로세서로 동작한다. 포괄적인 검증을 위하여 명령어 단위의 검증 뿐 아니라 최대/최소 검색, 이상/이하 검색, 병렬 덧셈 등의 기본적인 병렬 알고리즘을 검증하였으며 알고리즘은 처리 데이터의 개수와는 무관한 상수의 복잡도 O(k)를 갖으며 데이터의 비트 수만큼의 이터레이션을 갖는다.

• IEIE Transactions on Smart Processing and Computing
• /
• v.6 no.2
• /
• pp.133-139
• /
• 2017

Vehicles have increasingly evolved and become intelligent with convergence of information and communications technologies (ICT). Vehicle communications (VC) has become one of the major necessities for intelligent vehicles. However, VC suffers from serious security problems that hinder its commercialization. Hence, the IEEE 1609 Wireless Access Vehicular Environment (WAVE) protocol defines a security service for VC. This service includes Advanced Encryption Standard-Counter with CBC-MAC (AES-CCM) for data encryption in VC. A high-speed AES-CCM crypto module is necessary, because VC requires a fast communication rate between vehicles. In this study, we propose and implement an efficient AES-CCM hardware architecture for high-speed VC. First, we propose a 32-bit substitution table (S_Box) to reduce the AES module latency. Second, we employ key box register files to save key expansion results. Third, we save the input and processed data to internal register files for secure encryption and to secure data from external attacks. Finally, we design a parallel architecture for both cipher block chaining message authentication code (CBC-MAC) and the counter module in AES-CCM to improve performance. For implementation of the field programmable gate array (FPGA) hardware, we use a Xilinx Virtex-5 FPGA chip. The entire operation of the AES-CCM module is validated by timing simulations in Xilinx ISE at a speed of 166.2 MHz.

• Journal of Broadcast Engineering
• /
• v.1 no.2
• /
• pp.152-164
• /
• 1996

This paper describes the hardware architecture and implementation trade-offs of the Grand Alliance HDTV video encoder system. The implemented video encoder accepts video in 1125 line(30Hz) interlaced format, and produces a bit-stream compliant with the motion picture experts group version 2(MPEG-2) standards. The encoder processing includes large- area motion estimation and an advanced rate control mechanism. To keep the system complexity realizable, we adopt a fast hierarchical motion estimation method and developed its hardware architecture. Furthermore an adaptive perceptual quantization method is adopted to improve the perceptual quality. The developed system Is based on the 4-way parallel processing architecture and is implemented by using programmable IC, memory IC, and special-purpose processors such as DCT and motion estimation processors.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.3
• /
• pp.232-239
• /
• 2010

By using the clock timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). Compared to the authors' prior work, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The delay block generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a $0.18\;{\mu}m$ CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors' prior work, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation.

• Korean Institute of Interior Design Journal
• /
• v.25 no.6
• /
• pp.79-88
• /
• 2016

The purpose of this study was to suggest ways to vitalize residential container architecture by identifying the building process of domestic residential container architecture and analyzing various problems appeared in the process and status of construction related to planning, design, and construction. Conclusion and suggestions of this study are as follows.; firstly, according to the current situation of domestic residential container architecture, the usage was planned mainly for accommodation. Secondly, For planning background of planning preparation stage, economic benefit for long-term residence individuality and diversity for long short term complex residence were the primary planning backgrounds. Thirdly, for floor planning of planning design stage, space planning for various purposes is necessary as creating inter-space, wide LDK space, and loft by using narrow and long container for the long-term residence. Lastly, For construction stage, ways to reduce personnel expenses are being required by reducing the term of works and simplifying the processing stage by running factory production and field construction in parallel. If reduction method of construction cost through energy saving and mass production system is considered in the future, it would be possible to expand the development to dormitory and community housing for university students who are pressured by housing cost.

• Journal of KIISE:Computer Systems and Theory
• /
• v.31 no.1_2
• /
• pp.112-117
• /
• 2004

In this paper, we propose a suitable multiplication architecture for cellular automata in a finite field $GF(2^m)$. Proposed least significant bit first multiplier is based on irreducible all one Polynomial, and has a latency of (m+1) and a critical path of $ 1-D_{AND}＋1-D{XOR}$.Specially it is efficient for implementing VLSI architecture and has potential for use as a basic architecture for division, exponentiation and inverses since it is a parallel structure with regularity and modularity. Moreover our architecture can be used as a basic architecture for well-known public-key information service in $GF(2^m)$ such as Diffie-Hellman key exchange protocol, Digital Signature Algorithm and ElGamal cryptosystem.

• Journal of information and communication convergence engineering
• /
• v.15 no.1
• /
• pp.62-71
• /
• 2017

This paper presents a low-power voltage converter based on a reconfigurable capacitor array. Its energy recycling capacitor array stores the energy during a charge stage and supplies the voltage during an energy recycle stage even after the power source is disconnected. The converter reconfigures the capacitor array step-wise to boost the lost voltage level during the energy recycle stage. Its energy saving is particularly effective when most of the energy remaining in the charge capacitors is wasted by the leakage current during a longer sleep period. Simulations have been conducted using a voltage source of 500 mV to supply a $V_{DD}$ of around 800 mV to a load circuit consisting of four 32-bit adders in a 65-nm CMOS process. Results demonstrate energy recycling efficiency of 85.86% and overall energy saving of 40.14% compared to a conventional converter, when the load circuit is shortly active followed by a long sleep period.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.3C
• /
• pp.228-236
• /
• 2006

A Multicarrier code division multiple access(MC-CDMA) is a scheme that combines multicarrier modulation with CDMA. It offers robustness to frequency selective fading effect and can support higher rate data transmission with higher spectral efficiency. The objective of this article is proposed and analyzed a new asynchronous MC-CDMA system with various kinds of data rates which employs a multiple access interference (MAI) canceller. The proposed multirate MC-CDMA system can be accomplished by changing the number of Parallel branch(P) according to their data rate and hybrid interference canceller(HIC) are used for MAI cancellation. We compare the performance of proposed system in terms of average bit error rate(BER) with that of a single rate MC-CDMA system. The results show the large improvement in performance that can be attained by the cancellation scheme under multipath environments.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.10
• /
• pp.186-194
• /
• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• Journal of IKEEE
• /
• v.11 no.2
• /
• pp.83-88
• /
• 2007

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The 8${\times}$8 multiplier is designed with proposed MCML full adders and conventional full adders. The designed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. This circuit is designed with Samsung 0.35${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.