• 한국통신학회논문지
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• 제26권4B호
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• pp.520-527
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• 2001

육상이동위성 채널에서 고속 광대역의 정보를 효율적으로 전송하기 위한 최적 방안으로 OFDM(Orthogonal Frequency Division Multiplexing) M-ary PSK를 들 수 있다. 그러나 가입자 단말기 또는 위성중계기의 송신단 고출력 증폭기(HPA : High Power Amplifier)를 전력효율적인 비선형 mode에서 동작할 때, OFDM M-ary PSK 시스템의 최대 전력 대 평균전력의 비(PAPR : Peak-to-Average Power Ratio)가 부바송파 개수만큼 선형적으로 커져 단일 반송파 변조방식에 비해 비선형 왜곡에 의한 성능 열화가 심각하다. 본 논문에서는 이와 같은 성능 열화를 개선하기 위하여 전송채널에서 대역효율과 BER(Bit Error Rate) 성능이 우수한 PC(Parallel Combinatory) OFDM 방식과 개선된 PAPR을 가지는 PTS(Partial Transmit Sequence) OFDM 방식을 결합한 Combined PC & PTS OFDM 방식을 제안하고 그 성능을 분석하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 D
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• pp.2992-2994
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• 2005

수십 센티미터 이내의 오차를 만족시키는 거리/위치판별 기능 및 저속 데이터 송수신 기능 구현을 주목적으로 발족된 저속 무선 개인영역 네트워크(LR-WPAN: Low Rate Wireless Personal Area Network)의 표준인 IEEE802.15.4a는 간단하고 경제적이며 전력 소모가 적은 송수신기 구조를 요구한다. 이에 본 논문에서는 PEWB(Parallel Energy Window Banks)를 이용한 독창적인 비동기(noncoherent) OOK(On-Off Keying) UWB(Ultra-Wide Band) 송수신기 구조를 제안한다. 또한 무선 다중경로 채널상황을 다소 극복할 수 있는 펄스와 비트 반복 기법을 사용한다. 제안된 송수신기의 잡음 특성 분석을 위해 chi-square 분포가 사용되며, 반복적 계산을 통해 얻어진 임계값을 적용하여 BER(Bit Error Rate) 성능을 분석한다.

• 전자공학회논문지A
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• 제30A권8호
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• pp.1-10
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• 1993

In this paper, we will propose 4-move ZKIP and its application. Using bit-commitment scheme that is necessary to organize the ZKIP related to NP-Complete problem and WH and WI preserving the property for security under parallel composition of protocols, we will show that the proposed ZKIP is 4-move ZKIP of SAT comparing to 6-move ZKIP of SAT proposed by Brassard. Chaum and Yung, and under claw-free pairs of function the proposed ZKIP is also 4-move ZKIP comparing to 5-move ZKIP proposed by Goldreich and Krawczyk under the same assumption. Moreover we will show the efficiency of the proposed scheme better than Fiat and Shamir's scheme at the points of computational complexity and communication complexity, and also propose the efficient and secure identification scheme against the chosen ciphertext attack, using the proposed scheme.

• Journal of information and communication convergence engineering
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• 제15권4호
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• pp.212-216
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• 2017

In this paper, we introduce novel techniques to improve the high performance of AE functions on modern high-end IoT platforms (ARM-NEON), which support SIMD and cryptography instruction sets. For the Sophie Germain Counter Mode of operation (SGCM), counter modes of encryption and prime field multiplication are required. We chose the Montgomery multiplication for modular multiplication. We perform Montgomery multiplication in a parallel way by exploiting both the ARM and NEON instruction sets. Specifically, the NEON instruction performed 128-bit integer multiplication and the ARM instruction performed Montgomery reduction, simultaneously. This approach hides the latency for ARM in the NEON instruction set. For a high-speed counter mode of encryptions for both AE functions, we introduced two-level computations. When the tasks were large volume, we switched to the NEON instruction to execute the encryption operations. Otherwise, we performed the encryptions on the ARM module.

• 한국통신학회논문지
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• 제21권5호
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• pp.1332-1344
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• 1996

This paper presents a pipelined floating point multiplier(FMUL) for superscalar microprocessors that conbines radix-16 recoding scheme based on signed-digit(SD) number system and new rouding and normalization scheme. The new rounding and normalization scheme enable the FMUL to compute sticky bit in parallel with multiple operation and elminate timing delay due to post-normalization. By expoliting SD radix-16 recoding scheme, we can achieves further reduction of silicon area and computation time. The FMUL can execute signle-precision or double-precision floating-point multiply operation through three-stage pipelined datapath and support IEEE standard 754. The algorithm andstructure of the designed multiplier have been successfully verified through Verilog HOL modeling and simulation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.173-176
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• 2002

This paper is about a high-speed MAC (multiplier and accumulator) design applying radix-4 and radix-8 Booth's algorithm at the same time. The optimized hybrid radix design for high speed MAC has taken advantage of both a radix-4 and a radix-8 architectures. A radix-4 architecture meets high-speed, but it takes much more power and chip area than a radix-8 architecture. A radix-8 architecture needs less power and chip area than the other, but it has a bottleneck of generating three times the multiplicand problem. An optimized hybrid architecture performs the radix-4 multiplication partially in parallel with the generation of three times the multiplicand for use of the radix-8 multiplication. It reduces the concerned bit width of multiplier in radix-8 multiplication.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1137-1140
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• 2003

The area of the prototype device is less than 80mm$^2$. Operating with a 60ns clock cycle, the device typically dissipates only 300mW. The full functionality was proven by using the methodical test programs based on typical image processing operations. Also, we realized the whole process from conventional gray image to color image. Format converters, implemented using multidimensional access memories, transfer the data between the processing element array and conventional bit-parallel components in real time. The completed system is fully functional and performs typical low-level image processing tasks at speed exceeding 30 frames of traditional TV system per second.

• 전자공학회논문지A
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• 제32A권5호
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• pp.71-80
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• 1995

The usual approach for desinging a fast multiplier involves finding a way to quickly add up all the partial products, based on parital product recoding scheme and carry-save addition. This paper describes theoretical medels for area and time complexities of Multibit Reconding Paralle Multiplier (MRPM), which is a generalization of the modified Booth recoding scheme. Based on the proposed models, time performance, hardware requirements and area-time efficiency are analyzed in order to determine optimal recoding size for very large scale integration (VLSI) realization of the MRPM. Some simulation results show that the MRPM with large multiplier and multiplicand size has optimal area-time efficiency at the recoding size of 4-bit.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• Journal of applied mathematics & informatics
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• 제29권1_2호
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• pp.247-255
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• 2011

Invertible functions with a single cycle property have many cryptographic applications. The main context in which we study them in this paper is pseudo random generation and stream ciphers. In some cryptographic applications we need a generator which generates binary sequences of period long enough. A common way to increase the size of the state and extend the period of a generator is to run in parallel and combine the outputs of several generators with different period. In this paper we will characterize a secure quadratic polynomial on $\mathbb{Z}_{2^n}$, which generates a binary sequence of period long enough and without consecutive elements.