• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.29-37
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• 1997

A new algorithm and parallel architecture for high-speed complex number multiplication is presented, and a prototype chip based on the proposed approach is designed. By employing redundant binary (RB) arithmetic, an N-bit complex number multiplication is simplified to two RB multiplications (i.e., an addition of N RB partial products), which are responsible for real and imaginary parts, respectively. Also, and efficient RB encoding scheme proposed in this paper enables to generate RB partial products without additional hardware and delay overheads compared with binary partial product generation. The proposed approach leads to a highly parallel architecture with regularity and modularity. As a results, it results in much simpler realization and higher performance than the classical method based on real multipliers and adders. As a test vehicle, a prototype 8-b complex number multiplier core has been fabricated using $0.8\mu\textrm{m}$ CMOS technology. It contains 11,500 transistors on the area of about $1.05 \times 1.34 textrm{mm}^2$. The functional and speed test results show that it can safely operate with 200 MHz clock at $V_{DD}=2.5 V$, and consumes about 90mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.1A
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• pp.47-53
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• 2003

This paper describes the design of a 155 Mb/s multiplexer-demultiplexer chip. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s serial data output, and is to deinterleave a serial input bit stream of 155 Mb/s into the parallel output of 51 Mb/s The input and output of the device are TTL compatible at the low-speed end, but 100K ECL compatible at the high-speed end The device has been fabricated with a 0.7${\mu}m$ BiCMOS gate array The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 470 ps at the high-speed end. And power dissipation is evaluated under 2.0W.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.147-150
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• 2007

This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16$\times$16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35$\mu$m standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.7
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• pp.657-666
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• 2002

In this paper, a new broadband phase shifter to adjust the slope of dispersive phase characteristic for frequency of transmission network was proposed. The new fundamental network consists of a fixed main line with a length of λ/2 at the center frequency and two double stubs, each with a length of λ/8 at the center frequency, which are open and shorted, respectively, and which are shunted at the edge points of the main line. Characteristic impedances of the main line and two parallel double stubs are adjusted to produce a minimum phase error and to obtain an input and output match at the desired phase shift. Especially, the proposed structure is especially suitable for a broadband phase shifter with large phase shifts more than 90$^{\circ}$, and it is operated in the octave bandwidth. To verify the usefulness of a new broadband phase shifter, each 45$^{\circ}$-, 90$^{\circ}$-, 180$^{\circ}$-bit phase shifter and 3-bit phase shifter(45$^{\circ}$-phase step), which is cascaded in series, operated at the center frequency 3 GHz were designed, fabricated and experimented. The measured results were in very close agreement with the corresponding simulation results over the bandwidth of I/O impedance match and phase error for each phase shift.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.45-52
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• 2002

In this contributions, we propose a new MSB(most significant bit) algorithm based on AOP(All One Polynomial) and two parallel semi-systolic architectures to computes $AB^2$over finite field $GF(2^m)$. The proposed architectures are based on standard basis and use the property of irreducible AOP(All One Polynomial) which is all coefficients of 1. The proposed parallel semi-systolic architecture(PSM) has the critical path of $D_{AND2^+}D_{XOR2}$ per cell and the latency of m+1. The modified parallel semi-systolic architecture(WPSM) has the critical path of $D_{XOR2}$ per cell and has the same latency with PSM. The proposed two architectures, PSM and MPSM, have a low latency and a small hardware complexity compared to the previous architectures. They can be used as a basic architecture for exponentiation, division, and inversion. Since the proposed architectures have regularity, modularity and concurrency, they are suitable for VLSI implementation. They can be used as a basic architecture for algorithms, such as the Diffie-Hellman key exchange scheme, the Digital Signature Algorithm(DSA), and the ElGamal encryption scheme which are needed exponentiation operation. The application of the algorithms can be used cryptosystem implementation based on elliptic curve.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.5
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• pp.504-514
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• 2014

An MMIC multi-function chip with a low DC power consumption for an X-band active phased array radar system has been designed and fabricated using a 0.5 ${\mu}m$ GaAs p-HEMT commercial process. The multi-function chip provides several functions: 6-bit phase shifting, 6-bit attenuation, transmit/receive switching, and signal amplification. The fabricated multi-function chip with a compact size of $16mm^2(4mm{\times}4mm)$ exhibits a gain of 10 dB and a P1dB of 14 dBm from 7 GHz to 11 GHz with a DC low power consumption of only 0.6 W. The RMS(Root Mean Square) errors for the 64 states of the 6-bit phase shift and attenuation were measured to $3^{\circ}$ and 0.6 dB, respectively over the frequency.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.291-298
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• 2023

SRAM-based in-memory computing is one of the technologies to solve the bottleneck of von Neumann architecture. In order to achieve SRAM-based in-memory computing, it is essential to design efficient SRAM bit-cell. In this paper, we propose a low-power differential sensing 8+T SRAM bit-cell which reduces power consumption and improves circuit performance. The proposed 8+T SRAM bit-cell is applied to ripple carry adder which performs SRAM read and bitwise operations simultaneously and executes each logic operation in parallel. Compared to the previous work, the designed 8+T SRAM-based ripple carry adder is reduced power consumption by 11.53%, but increased propagation delay time by 6.36%. Also, this adder is reduced power-delay-product (PDP) by 5.90% and increased energy-delay- product (EDP) by 0.08%. The proposed circuit was designed using TSMC 65nm CMOS process, and its feasibility was verified through SPECTRE simulation.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.6
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• pp.48-56
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• 2010

Recently, we need to dramatically speed up real-time video encoding and decoding on mobile devices because complexity of video CODEC is significantly increasing along with the demand for multimedia service of high-quality and high-definition videos by users. A variety of research is conducted for parallelism of video processing using newly developed multi-core platforms. In this paper, we propose a method of parallelism based on slice partition of video compression CODEC. We propose a novel concept of a parallel slice for parallelism and propose a new coding order to be adequate to the parallel slice which keeps high coding efficiency. To minimize synchronization time of multiple parallel slices, we also propose a synchronization method to determinate whether the parallel slice could be independently decoded or not. Experimental results shows that we achieved 27.5% (40.7%) speed-up by parallelism with bit-rate increase of 3.4% (2.7%) for CIF sequences (720p sequences) by implementing the proposed algorithm on the H.264/AVC.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.1
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• pp.17-27
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• 2005

In this paper, we introduce a Parallel Interference Canceller (PIC) based sorting method to improve performance in the MC-DS/CDMA environment. A conventional PIC estimates and subtracts out all of the MAI (Multiple Access Interference) for each user in parallel. The parallel process ensures the low delay for the detection of all users. Also this scheme requires more stages for having better performance. Since the performance of PIC is strongly related to the correct MAI estimation, we introduce the IC (Interference Cancellation) scheme to estimate the accurate weaker signal group than the desired signal using conventional PIC. The principle of the proposed receiver sorts in descending order by the strength of signal and subtracts the MAI of the strong interferers from the desired signal for the accurate estimate of the weaker signals. Following this, the proposed scheme cancels out the improved weaker interference from the desired signal, using the output of the pre-step. In this result, the proposed system obtains better BER performance than the conventional PIC because the accuracy of the strong signal is improved. However, a disadvantage exists in that the processing time has slightly longer delay than the PIC owing to the power sorting and the MAI estimation process. The system performance evaluates and compares other non-liner It according to the number of sub-carriers in the limited-bandwidth.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.13-20
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• 2008

This paper describes the design of low power 12bit Digital-to-Analog Converter(D/A Converter) using Pseudo-Segmentation method which shows the conversion rate of 80MHz and the power supply of 1.8V with 0.18um CMOS n-well 1-poly 6-metal process for advanced wireless communication system. Pseudo-segmentation method used in binary decoder consists of simple parallel buffer is employed for low power because of simpler configuration than that of thermometer decoder. Also, using deglitch circuit and swing reduced drivel reduces a switching noise. The measurement results of the proposed low power 12bit 80MHz CMOS D/A Converter shows SFDR is 66.01dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB is 10.67bit. Integral nonlinearity(INL) / Differential nonlinearity(DNL) have been measured ${\pm}1.6LSB/{\pm}1.2LSB$. Glich energy is measured $49pV{\cdot}s$. Power dissipation is 46.8mW at 80MHz(Maximum sampling frequency) at a 1.8V power supply.