• 대한전자공학회논문지SD
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• 제45권12호
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• pp.29-40
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• 2008

유한체 GF($2^n$) 연산을 바탕으로 구성되는 암호시스템에서 유한체 곱셈의 효율적인 하드웨어 설계는 매우 중요한 연구분야이다. 본 논문에서는 공간 복잡도가 낮은 병렬 처리 유한체 곱셈기를 구성하기 위하여 삼항 기약다항식(Trinomial) $f(x)=x^n+x^k+1$의 모듈러 감산 연산 특징을 이용하였다. 또한 연산 수행 속도를 빠르게 개선하기 위해 하드웨어 구조를 기존의 Mastrovito 곱셈 방법과 유사하게 구성한다. 제안하는 곱셈기는 $n^2-k^2$ 개의 AND 게이트와 $n^2-k^2+2k-2$개의 XOR 게이트로 구성되므로 이는 기존의 $n^2$ AND게이트, $n^2-1$ XOR 게이트의 합 $2n^2-1$에서 $2k^2-2k+1$ 만큼의 공간 복잡도가 감소된 결과이다. 시간 복잡도는 기존의 $T_A+(1+{\lceil}{\log}_2(2n-k-1){\rceil})T_X$와 같거나 $1T_X$ 큰 값을 갖는다. 최고차 항이 100에서 1000 사이의 모든 기약다항식에 대해 시간복잡도는 같거나 $1T_X(10%{\sim}12.5%$)정도 증가하는데 비해 공간 복잡도는 최대 25% 까지 감소한다.

• 한국전자파학회논문지
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• 제22권6호
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• pp.613-624
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• 2011

본 논문에서는 X-대역 능동 위상 배열 레이더 시스템용 MMIC 다기능 칩을 0.5 ${\mu}m$ p-HEMT 상용 공정을 이용하여 개발하였다. 설계된 다기능 칩에는 제어 신호 선로수를 최소화하기 위해 디지털 직병렬 변환기를 포함하고 있다. 다기능 칩은 6-비트 디지털 위상 천이 기능, 6-비트 디지털 감쇠 기능, 송/수신 모드 선택 기능, 신호 증폭 기능 등의 다양한 기능을 제공한다. 24 $mm^2$(6 mm${\times}$4 mm) 칩 크기의 비교적 소형으로 제작된 MMIC 다기능 칩은 8.5~10.5 GHz에서 24/15 dB의 송/수신 이득 특성과 21 dBm의 P1dB 특성을 보였다. 그리고 6-비트, 64 상태에 대해 위상 천이 특성과 감쇠 특성의 측정 결과, 동작 주파수에서 $7^{\circ}$의 RMS 위상 오차와 0.3 dB의 RMS 감쇠 오차를 보였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.771-774
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• 1998

In this paper proposes a new bit-parallel structure for a multiplier over GF((Pn)m), with k-nm. Mastrovito Multiplier, Karatsuba-ofman algorithm are applied to the multiplication of polynomials over GF(2n). This operation has a complexity of order O(k log p3) under certain constrains regardig k. A complete set of primitive field polynomials for composite fields is provided which perform modulo reduction with low complexity. As a result, multiplier for fields GF(Pk) with low gate counts and low delays are constructed. The architectures are highly modular and thus well suited for VLSI implementation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.871-872
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• 2008

The method and results of the software implementation of a echo processor for medical ultrasound imaging using a GPU (NVIDIA G80) is presented. The echo signal processing functions are modified in a SIMD manner suitable for the GPU's massively parallel processing architecture so that the GPU's 128 ALUs are utilized nearly 100%. The preliminary result for a frame of image composed of 128 scan lines, each having 10240 16-bit samples, shows that the echo processor can be inplemented at a high rate of 30 frames per second when implemented in C, which is close to the optimized assembly codes running on the TI's TMS320C6416 DSP.

• 대한전자공학회논문지
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• 제27권6호
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.333-336
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• 1999

In this paper, a new high speed parallel input and parallel output GF(2$^{m}$ ) multiplier based on standard basis is proposed. The concept of the multiplication in standard basis coordinates gives an easier VLSI implementation than that of the dual basis. This proposed algorithm and method of implementation of the GF(2$^{m}$ ) multiplication are represented by two kinds of basic cells (which are the generalized and fixed basic cell), and the minimum critical path with pipelined operation. In the case of the generalized basic cell, the proposed multiplier is composed of $m^2$ basic cells where each cell has 2 two input AND gates, 2 two input XOR gates, and 2 one bit latches Specifically, we show that the proposed multiplier has smaller complexity than those proposed in 〔5〕.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.697-700
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• 2002

In this paper, we proposed the micro web-server Implementation on Strong ARM processor with embedded Linux. The parallel port connecting parallel I/O is controlled via HPPT protocol and web browser program. HTTP protocol is ported into Linux and the micro web server program and port control program are installed on-board memory using CGI to be accessed by web browser, such as Internet Explore and Netscape. 8bit LED and DIP switches are connected to the processor port and the switch input status is monitored and the LED output is controlled from remote hosts vie internet. The result of the proposed embedded micro-web server can be used in automation systems, remote distributed control via internet using web browser.

• The Journal of the Acoustical Society of Korea
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• 제14권2E호
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• pp.50-56
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• 1995

본 논문은 3가지 상태의 전이 그래프를 이용해서, 병렬 컴퓨터인 MasPar에 적합한 한글에 대한 효율적인 부호화를 제시하고자 한다. 본 논문에서 제시한 PHDCM(Parallel Hangul Dynamic Coding Method)의 방법을 이용한 경우에 한글 한음절당 약 3.5비트이상의 축약이 가능함을 보였다. 그리고 기존의 방법과 비교해 볼때 1비트이상의 축약이 가능함도 보였다. 또한 약 천만자의 한글을 이용해서, 병렬 컴퓨터인 MasPar에 프로세서 64개를 이용하여 실제 실행을시켰을때의 가속도 (Speedup)은 49.314임을 보였다.

• Current Optics and Photonics
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• 제1권4호
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• pp.289-294
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• 2017

A high-performance time-division multiplexing (TDM) -based multiuser (MU) multiple-input multipleoutput (MIMO) system for efficient indoor visible-light communication (VLC) is presented. In this work, a MIMO technique based on RGB light-emitting diodes (LEDs) with selection combining (SC) is utilized for data transmission. That is, the proposed scheme employs RGB LEDs for parallel transmission of user data and transmits MU data in predefined slots of a time frame with a simple and efficient design, to schedule the transmission times for multiple users. Simulation results demonstrate that the proposed scheme offers an approximately 6 dB gain in signal-to-noise ratio (SNR) at a bit error rate (BER) of $3{\times}10^{-5}$, as compared to conventional MU single-input single-output (SISO) systems. Moreover, a data rate of 66.7 Mbps/user at a BER of $10^{-3}$ is achieved for 10 users in indoor VLC environments.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2006년도 International Symposium on GPS/GNSS Vol.2
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• pp.261-266
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• 2006

A number of different techniques are available to mitigate the problem of cross correlations caused by the limited dynamic range of the 10-bit Gold codes in the GPS C/A code. These techniques include successive-interference cancellation (SIC) and parallel-interference cancellation (PIC), where the strong signals are subtracted at IF prior to attempting to detect the weak signals. In this paper, a variation of these techniques is proposed whereby the subtraction process is delayed until after the correlation process, although still employing a pure reconstructed C/A code signal to permit prediction of the cross correlation process. The paper provides details on the method as well as showing the results obtained when the method was implemented using a software GPS receiver. The benefits of this approach are also described, as is the application of the method to the cancellation of CW interference.