• Journal of Convergence for Information Technology
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• v.11 no.8
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• pp.1-7
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• 2021

In this paper, a method of extending 1 bit by adding an external device to a parallel interface type Digital-to-Analog conversion(D/A C) circuit is presented. To do this, the principle of the D/A C circuit was examined, and the problems that occur when extending one bit by adding individual devices were analyzed, and a bit extension method of the D/A devices using an OP-Amp. circuit was presented. As the proposed method uses the high-precision characteristics of the OP-Amp., even if an error occurs in the device, only the overall size of the output waveform is affected, and the voltage reversal phenomenon that occurs between each bit does not occur. In order to confirm the effect of the proposed method, an experimental circuit was constructed and the absolute voltage of the output and the relative error were measured. As a result, a voltage error of 0.0756% appeared, confirming that the 0.195% requirement for one bit expansion by adding individual devices was sufficiently satisfied.

• Journal of Korea Multimedia Society
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• v.14 no.5
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• pp.650-657
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• 2011

This paper proposes a novel bit allocation algorithm for H.264 scalable extension(SE) based on a human visual system (HVS) to improve the coding efficiency. The proposed algorithm is consist of two stages: visual weighting model and visual weighting-based bit allocation algorithm. In the first stage, the visual weighting for each macroblock (MB) is analyzed according to the region of interests. Then the adaptation of the visual weighting into the bit allocation routine for each quality layer is performed for improving the visual quality. In the simulation results, it is observed that the proposed scheme can improve the subjective and objective video quality in the same bit rate, compared to the previous scalable video coding in H.264.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.48-57
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• 2003

In this paper, An 8${\times}$l ID-IDCT processor with adder-based distributed arithmetic(DA) and bit-serial method Is presented. To reduce hardware cost and to improve operating speed, the proposed 8${\times}$1 ID-IDCT used the bit-serial method and DA method. The transform of coefficient equation results in reduction in hardware cost and has a regularity in implementation. The sign extension computation method reduces operation clock. As a result of logic synthesis, The gate count of designed 8${\times}$1 1D-IDCT is 17,504. The sign extension processing block has gate count of 3,620. That is 20% of total 8${\times}$1 ID-IDCT architecture. But the sign extension processing block improves more than twice in throughput. The designed IDCT processes 50Mpixels per second and at a clock frequency of 100MHz.

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.730-737
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• 2013

In this paper, Constrained One-Bit Transform (C1BT) based motion estimation using extension of matching error criterion is proposed. C1BT based motion estimation algorithm exploiting Number of Non-Matching Points (NNMP) instead of Sum of Absolute Differences (SAD) that used in the Full Search Algorithm (FSA) facilitates hardware implementation and significantly reduces computational complexity. However, the accuracy of motion estimation is decreased. To improve inaccurate motion estimation, this algorithm based motion estimation extending matching error criterion of C1BT is proposed in this paper. Experimental results show that proposed algorithm has better performance compared with the conventional algorithm in terms of Peak-Signal-to-Noise-Ratio (PSNR).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.724-730
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• 2017

SpaceWire invented for spacecrafts has Time-Code defined for time synchronization over SpaceWire network. A Time-Code suffers transmission delay of 14[bit-period] and jitter up to 10[bit-period] whenever it passes through a SpaceWire link, which is the primary cause of time synchronization error. This work presents a simple method to improve the time synchronization which uses two extended Time-Codes. Nodes on a SpaceWire network can find how much delay and jitter a received Time-Code has suffered while it passes through the network, and they can correct time synchronization error with this information. The proposed method was validated in a simulation environment developed based on OMNeT++. The simulation result showed that time synchronization error less than a few bit-periods can be achieved. The proposed method is cost effective and suitable for small-scale SpaceWire network systems.

• Journal of Information Technology Services
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• v.12 no.1
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• pp.1-14
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• 2013

The government has implemented operating the bus information terminal (hereinafter, 'BIT') to use by building it at a major bus station to solve the problem of traffic congestion. Busan Metropolitan City has been continuously expanding the installation of 'BIT' since 2003. However, there are few research on the factor to use and satisfaction survey on 'BIT' from the perspective of the users. This study, in an effort to inquire into the 'BIT' utilization factor and its vitalization plan, conducted a face to face survey of 172 citizens who had the experience in the 'BIT'. The result of the data analysis showed that usability, convenience, and availability were the critical factors for a BIT use. In addition, the general intention to use 'BIT' was found to be very high as much as 90.7%. The contributions of this study are as follows. The academic contributions is that it proved the relationship between usability, convenience and the intention to use suggested by the information technology acceptance model is supported even in case of 'BIT.' For the practitioners this study provides ground data for a local government to make a plan of a BIT extension.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.124-130
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• 2015

This paper presents a high performance HIGHT processor that can be applicable for CCM mode. In fact, HIGHT algorithm is a 64-bit block cipher. However, the proposed HIGHT extends the basic block length to 128-bit. The proposed HIGHT is operated as 128-bit block cipher and it can treat 128-bit block at once. Thus, it can be applicable for the various WSN applications that need fast and ultralight 128-bit block cipher, in particular, to be operated in CCM mode. In addition, the proposed HIGHT processor shares the common logics such as 128-bit key scheduler and control logics during encryption and decryption to reduce the area overhead caused by the extension of data block length. From the simulation results, the circuit area and power consumption of the proposed HIGHT are increases as 40% and 64% compared to the conventional 64-bit counterpart. However, the throughput of the proposed HIGHT can be up to two times as fast. Consequently, the proposed HIGHT is useful for USN and handheld devices based on battery as well as RFID tag the size of circuit is less than 5,000 gates.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.11
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• pp.9-14
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• 2008

This paper presents the performance analysis of 10[Gb/s] optical duobinary transmitters with the non-ideal Mach-Zehnder modulator which does not have exactly 50/50 splitting/combining ratios by computer simulations. For driving voltage ratios(=driving voltage/switching voltage) with smaller than 100[%], the transmission performance has been greatly affected by extension of LPF bandwidths. Nevertheless, the performance has been degraded when the driving voltage ratio is 100[%]. The smaller driving voltage ratios has, the more sensitivity improves by extension of LPF bandwidths under the asymmetry condition. But the driving voltage ratio with 80[%] has better bit error rate(BER) than those with 50[%] and 25[%].

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.309-322
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• 2021

In this study, an extension instruction set for high-speed operation of the ARIA block cipher algorithm on RISC-V processor is added to support high-speed cryptographic operation on low performance IoT devices. We propose the efficient ARIA cryptographic instruction set which runs on a conventional 32-bit processor. Compared to the existing software cryptographic operation, there is a significant performance improvement with proposed instruction set.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.8
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• pp.15-21
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• 1996

This paper describes data placement schemes that provide uniform and balanced to multiple disks load for retrievals of VBR (variable bit rate) video at varying retrieval speeds. To support maximum concurent users at arbitrary-speed playbacks in a disk-arry based system, the hot spot disks should be carefully avoided. In this paper, we extend the proposed scheme, prime round-robin(PRR), for VBR video. In addition, we have compared the performance of PRR and PRR (PRR extension).