• Journal of Satellite, Information and Communications
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• v.10 no.3
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• pp.73-77
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• 2015

In this paper, we present two simulation methods to investigate the effect of excluding bit errors on generating the extrinsic information transfer (EXIT) chart for low density parity check (LDPC) and turbo codes. We utilized the simulation methods including and excluding bit errors to generate EXIT chart which was originally proposed for turbo codes. The generated EXIT charts for LDPC and turbo codes shows that the presented methods appropriately demonstrates the performance behaviours of iterative decoding for LDPC and turbo codes. Analysis on the simulation results demonstrates that the EXIT chart excluding the bit errors shows only a small part of the curves where the amount of information is too large.

• Journal of Communications and Networks
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• v.8 no.4
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• pp.391-400
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• 2006

With the on-going wireless access technologies, the Internet has become accessible anytime anywhere. In wireless networks, link errors significantly degrade the performance of the transmission control protocol (TCP). To cope with this issue, this paper improves the recently-proposed terrestrial REFWA (T-REFWA) scheme by adding a new error recovery mechanism to its original design. In the T-REFWA scheme, senders are acknowledged with appropriate sending rates at which an efficient and fair utilization of network resources can be achieved. As the feedback values are computed independently of link errors, senders can keep transmitting data at high rates even in case of link error occurrences. Using this feature, the proposed error recovery mechanism can achieve high throughput in environments with high bit error rates. The throughput is further improved by disabling the exponential back-off algorithm of TCP so that long idle times are avoided in case of link errors. We show through simulations that the proposed method improves TCP performance in high bit error rates. Compared with several TCP variants, the proposed error recovery scheme exhibits higher link utilization and guarantees system fairness for different bit error rates.

• Journal of Biomedical Engineering Research
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• v.7 no.1
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• pp.53-58
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• 1986

This paper represent the design of a digital modem which transmits the ECG data from an ambulatory arrhythmia monitor over the telephone lines to a large hospital for the instantaneous interpretations. The digital modem provides on-line communications between the patient and the central computer located near cardiologists. For commercial telephone lines, the transmitting error rates of the digital modem were measured 200 times at a speed of 300 baud. In those measurements, the block errors-results, due to the misinterpretation of start and stop bits, did not occur, The data bit errors which were due to a single bit interpreted incorrectly were 0.78 (bits/10 ) . Since the acceptable data bit error limit is 10 per 106 bits transmitted, the digital modem designed in this paper can be used for the clinical applications without any difficulty.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.3
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• pp.147-152
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• 1985

The error-trapping decoder is constructed for the (7, 3) Reed-Solomon code. The syndrome resister is constructed with the encoder and the substanial test logic circuits. The element of GF(8) is represented by the triple D-flip-floops. The hardware is constructed. And it is controlled by the micro computer(Apple II). The time for the encoding and the decoding were $350\musecs and 910u secs respectively. The experimental results show that the two symbol errors were corrected and 4-bit-binary-burst errors were also corrected.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.11
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• pp.1747-1750
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• 2022

As shrinking the semiconductor process into the deep sub-micron to achieve high-density, low power and high performance integrated circuits, MBU (multiple bit upset) by soft errors is one of the major challenge of on-chip memory systems. To address the MBU, single error correction, double error detection and double adjacent error correction (SEC-DED-DAEC) codes have been recently proposed. But these codes do not resolve mis-correction. We propose the SEC-DED-DAEC-TAED(triple adjacent error detection) code without mis-corrections. The generated H-matrix by the proposed heuristic algorithm to accomplish the proposed code is implemented as hardware and verified. The results show that there is no mis-correction in the proposed codes and the 2-stage pipelined decoder can be employed on-chip memory system.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.1
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• pp.101-105
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• 2008

This paper proposes an analytical model to calculate VoIP (Voice of IP) capacity over wireless LANs with frequent bit errors. Since the traditional analytical models for VoIP capacity have not included the effect of bit errors, simulations ould only evaluate VoIP capacity over erroneous channels. For analytically accurate estimation of VoIP capacity over noisy channels, we extend the conventional model to include the effect of propagation errors, end-to-end delay, voice quality, the waiting time in AP(Access Point). The experiments show that our model predicts the VoIP capacity of a given network within the range from 3% to 9% difference comparing with the simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6B
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• pp.948-953
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• 2010

In this paper, we propose multi-bit soft error detection method which can use an instruction cache of superscalar CPU architecture. Proposed method is applied to high-speed static RAM for instruction cache. Using 1D parity and interleaving, it has less memory overhead and detects more multi-bit errors comparing with other methods. It only detects occurrence of soft errors in static RAM. Error correction is treated like a cache miss situation. When soft errors are occurred, it is detected by 1D parity. Instruction cache just fetch the words from lower-level memory to correct errors. This method can detect multi-bit errors in maximum 4$\times$4 window.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.445-454
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• 2015

As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11C
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• pp.1030-1036
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• 2006

In this paper, we present two methods of correcting bit errors in constant amplitude multi-code (CAMC) CDMA, which uses the redundant bits only. The first method is a parity-based bit correction with hard-decision, where the received signals despread into n two-dimensional structure with both horizontal parity and vertical parity. Then, an erroneous bit is corrected for each $4{\times}4$ pattern. The second method is a turbo decoding, which is modified from the decoding of a single parity check product code (SPCPC). Experimental results show that, in the second method, the redundant bits in CAMC can be fully used for the error correction and so they are not really a loss of channel bandwidth. Hence, CAMC provides both a low peak-to-average power ratio and robustness to bit errors.

• Proceedings of the KIEE Conference
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• 2002.06a
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• pp.161-165
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• 2002

The paper presents a diagnostic tool for analyzing the bit intermodulation in D/A converter. Bit intermodulation cause linearity errors which degrade the performance of the converter. A linear transformation of the Walsh transform of the integrated non-linearity diagram is shown to be sufficient to extract the bit intermodulation terms and their noise sensitivity. Practical applicability of the proposed method is shown by measurement.