• Title/Summary/Keyword: Binomial tree option pricing model

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Option pricing and profitability: A comprehensive examination of machine learning, Black-Scholes, and Monte Carlo method

  • Sojin Kim;Jimin Kim;Jongwoo Song
    • Communications for Statistical Applications and Methods
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    • v.31 no.5
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    • pp.585-599
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    • 2024
  • Options pricing remains a critical aspect of finance, dominated by traditional models such as Black-Scholes and binomial tree. However, as market dynamics become more complex, numerical methods such as Monte Carlo simulation are accommodating uncertainty and offering promising alternatives. In this paper, we examine how effective different options pricing methods, from traditional models to machine learning algorithms, are at predicting KOSPI200 option prices and maximizing investment returns. Using a dataset of 2023, we compare the performance of models over different time frames and highlight the strengths and limitations of each model. In particular, we find that machine learning models are not as good at predicting prices as traditional models but are adept at identifying undervalued options and producing significant returns. Our findings challenge existing assumptions about the relationship between forecast accuracy and investment profitability and highlight the potential of advanced methods in exploring dynamic financial environments.

FPGA-Based Design of Black Scholes Financial Model for High Performance Trading

  • Choo, Chang;Malhotra, Lokesh;Munjal, Abhishek
    • Journal of information and communication convergence engineering
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    • v.11 no.3
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    • pp.190-198
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    • 2013
  • Recently, one of the most vital advancement in the field of finance is high-performance trading using field-programmable gate array (FPGA). The objective of this paper is to design high-performance Black Scholes option trading system on an FPGA. We implemented an efficient Black Scholes Call Option System IP on an FPGA. The IP may perform 180 million transactions per second after initial latency of 208 clock cycles. The implementation requires the 64-bit IEEE double-precision floatingpoint adder, multiplier, exponent, logarithm, division, and square root IPs. Our experimental results show that the design is highly efficient in terms of frequency and resource utilization, with the maximum frequency of 179 MHz on Altera Stratix V.