• Title/Summary/Keyword: Binary-CDMA

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Design and Performance Evaluation of Complex Spreading CDMA Systems for Improving Multiple Access Efficiency (다중 접속 효율 향상을 위한 Complex Spreading CDMA 시스템 설계와 성능 평가)

  • An, Changyoung;Ryu, Heung-Gyoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.11
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    • pp.1349-1355
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    • 2016
  • It should guarantee high reliability and ultra low latency communication. Additionally, it should support connection between massive devices. As one of estimated scenarios for 5G mobile communication, mobile devices and sensors using low data rate wireless communication will increase. For communication of these devices, single-carrier system can be considered. In order to satisfy these requirements, in this paper, we propose CDMA (Code Division Multiple Access) system using complex spreading and Multi-level BPSK(Binary Phase Shift Keying). The proposed system spread transmit symbol by using chip code consisted of real and imaginary number. As simulation results, we can confirm that although the proposed system has 3dB lower BER (Bit Error Rate) performance than conventional CDMA system, the proposed system can support 2 times more users in comparison with conventional CDMA system.

System of Binary CDMA memory structure for high data rate communication (고속 무선 데이터전송을 위한 바이너리 CDMA 데이터 버퍼 시스템)

  • Lim, Yong-Seok;Cho, Jin-Woong
    • Proceedings of the KAIS Fall Conference
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    • 2011.12b
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    • pp.668-670
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    • 2011
  • 본 논문에서는 고속 무선 데이터 전송을 위하여 멀티버스 구조 및 유연적인 데이터 버퍼시스템을 갖는 향상된 바이너리 CDMA에 시스템 설계에 관한 것이다. 개선된 바이너리 CDMA 시스템 구조는 제한된 리소스에서 시스템 버스의 Latency를 최대한 줄이고 고속 무선 데이터 전송을 위하여 버퍼접근구조를 변경하여 데이터 throughput을 향상하였다.

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A Study of Interference-Free Home PLC based on the Binary ZCD Code (연속직교 상관특성을 갖는 아진 코드 기반의 구내용 PLC에 관한 연구)

  • Cha, Jae-Sang;Kim, Seong-Kweon
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.20 no.2
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    • pp.38-44
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    • 2006
  • In this paper, a new interference-free Home CDMA-PLC(Code Division Multiple Access-Power Line Communication) system based on the binary ZCD(Zero Correlation Duration) spreading code is proposed as a key solution to overcome the previous problems. Binary ZCD spreading code sets with enlarged family sizes are generated by carrying out a chip-shift operation of the preferred pairs. The properties or the proposed ZCD-PLC systems are effective for MPI(Multi-Path Interference) and MAI (Multiple Access Interference) cancellation in the CDMA-PLC systems. By BER performance simulation, we certified the availability of proposed ZCD-CDMA-PLC system.

A Study on the Implementation of Low-speed Data Transmission System using Binary CDMA Technology (Binary CDMA 기술을 이용한 저속 데이터 전송시스템 구현방안에 관한 연구)

  • Kim, Yong-Seong;Cho, Jin-Woong;Lee, Hyeon-Seok
    • Proceedings of the KAIS Fall Conference
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    • 2011.12b
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    • pp.577-580
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    • 2011
  • 본 논문은 국내 순수 원천기술인 바이너리 CDMA 기술에 대하여 살펴보고, 이 기술이 적용된 Koinonia 시스템을 분석한다. 그리고 기존 고속의 Koinonia 시스템을 변경하여 동시에 운용할 수 있는 채널수를 최대화 하고 저속 데이터 전송시스템에 적용할 수 있는 기술을 제안한다. 또한 제안된 방법대로 테스트 베드를 구축하여 시험 및 검증함으로써 제안된 다채널 저속의 Koinonia 시스템을 다양한 산업응용분야에 적용시키고자 한다.

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A Study on the Generation of Frame Synchronization Words for W-CDMA System (W-CDMA 시스템을 위한 프레임 동기 단어 발생에 관한 연구)

  • 송영준
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.15 no.5
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    • pp.451-460
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    • 2004
  • The pilot bit pattern of W-CDMA system is used for the channel estimation and frame synchronization confirmation. This paper proposes the binary sequences for the frame synchronization for wideband code division multiple access (W-CDMA) system. We present the circuit for the generation of ideal frame synchronization property using the binary sequences called frame synchronization word(FSW). W-CDMA system uses compressed mode where up to 7 slots per one 10 msec frame are not transmitted to make measurements from another frequency without a full dual receiver terminal. It is shown that the proposed frame synchronization words also maintain the optimal frame synchronization property in the compressed mode by using the complementary mapping relationship of preferred pair. And we discuss the realization circuit for the generation of frame synchronization words by using the concept of preferred pairs, complementary mapping relationship, and maximal length sequence.

Home Networking System Employing Power Line and LED Lighting (전력선 및 LED 조명을 이용한 홈네트워킹 시스템)

  • Dan, Seungrok;Noh, Jinyoung;Lee, Seungwoo;Choi, Kyungmook;Ju, MinChul;Park, Youngil
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38C no.8
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    • pp.700-705
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    • 2013
  • If LED lighting is to be used in home networking, a home gateway and power line communication are needed in delivering data. In addition, an appropriate multiple access scheme reflecting LED's property is required. In this paper, a home networking system that can serve wide in-building area by integrating PLC and VLC, is proposed and implemented, then its performance is measured. A binary CDMA is used in the multiple access since this scheme is good for nonlinear device like LED, while infrared is used in the upstream transmission.

Design of High-Speed Correlator for a Binary CDMA (Binary CDMA를 위한 고속 코릴레이터 설계)

  • 구군서;정우경;문장식;류승문;이용석
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.787-790
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    • 2003
  • This paper describes a high speed correlator that can acquire synchronization quickly. The existing addition algorithm is a binary adder tree architecture that will result in extremely slow speed of operation due to many levels of logic required for computation of correlation[2][3]. This paper suggests the new various architectures, which are systolic array architecture, simple pipeline architecture and block systolic array architecture[4][5]. The acquisition performance of the proposed architectures is analyzed and compared with the existing architecture. The comparison results show that the systolic array architecture and the block systolic array architecture reduce the timing delay up to 73% and 31%, respectively. And the results show that the simple pipeline architecture reduces the timing delay up to 53%..

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An Improvement on FFT-Based Digital Implementation Algorithm for MC-CDMA Systems (MC-CDMA 시스템을 위한 FFT 기반의 디지털 구현 알고리즘 개선)

  • 김만제;나성주;신요안
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.7A
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    • pp.1005-1015
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    • 1999
  • This paper is concerned with an improvement on IFFT (inverse fast Fourier transform) and FFT based baseband digital implementation algorithm for BPSK (binary phase shift keying)-modulated MC-CDMA (multicarrier-code division multiple access) systems, that is functionally equivalent to the conventional implementation algorithm, while reducing computational complexity and bandwidth requirement. We also derive an equalizer structure for the proposed implementation algorithm. The proposed algorithm is based on a variant of FFT algorithm that utilizes a N/2-point FFT/IFFT for simultaneous transformation and reconstruction of two N/2-point real signals. The computer simulations under additive white Gaussian noise channels and frequency selective fading channels using equal gain combiner and maximal ratio combiner diversities, demonstrate the performance of the proposed algorithm.

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